RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA
R01UH0959EJ0110 Rev.1.10 Page 529 of 765
Mar 7, 2023
13.4.2 Setting transfer clock by using IICWL0 and IICWH0 registers
(1) Setting transfer clock on master side
Transfer clock =
At this time, the optimal setting values of the IICWL0 and IICWH0 registers are as follows.
(The fractional parts of all setting values are rounded up.)
●
In fast mode
IICWL0 =
0.52
Transfer clock
× f
IICWH0 =
0.48
Transfer clock
t
t
× f
●
In normal mode
IICWL0 =
0.47
Transfer clock
× f
IICWH0 =
0.53
Transfer clock
t
t
× f
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