RL78/G15 CHAPTER 6 TIMER ARRAY UNIT
R01UH0959EJ0110 Rev.1.10 Page 177 of 765
Mar 7, 2023
6.3 Registers Controlling Timer Array Unit
Timer array unit is controlled by the following registers.
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Peripheral enable register 0 (PER0)
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Timer clock select register m (TPSm)
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Timer mode register mn (TMRmn)
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Timer status register mn (TSRmn)
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Timer channel enable status register m (TEm)
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Timer channel start register m (TSm)
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Timer channel stop register m (TTm)
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Timer output enable register m (TOEm)
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Timer output register m (TOm)
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Timer output level register m (TOLm)
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Timer output mode register m (TOMm)
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Input switch control register (ISC)
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Noise filter enable registers 1 (NFEN1)
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Port mode control register (PMCxx)
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Port mode register (PMxx)
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Port register (Pxx)
Caution Which registers and bits are included depends on the product. Be sure to set bits that are not
mounted to their initial values.
Remark m: Unit number (m = 0), n: Channel number (n = 0 to 7)
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