RL78/G15 CHAPTER 8 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER
R01UH0959EJ0110 Rev.1.10 Page 308 of 765
Mar 7, 2023
8.3.1 Clock output select register 0 (CKS0)
This register enables or disables output from the pin for clock output or buzzer frequency output (PCLBUZ0) and sets the
output clock.
The CKS0 register is set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 8-2. Format of Clock Output Select Register 0 (CKS0)
Address: FFFA5H After reset: 00H R/W
Symbol
□
7 6 5 4 3 2 1 0
CKS0 PCLOE0 0 0 0 0 CCS02 CCS01 CCS00
PCLOE0 PCLBUZ0 pin output enable/disable specification
0 Output disable (default)
1 Output enable
CCS02 CCS01 CCS00 PCLBUZ0 pin output clock selection
f
MAIN
(MHz)
1 5 8 10 16
0 0 0 f
MAIN
1 MHz 5 MHz
Note 1
8 MHz
Note 1
10 MHz
Note 1
Setting
prohibited
Note 1
0 0 1 f
MAIN
/2 500 kHz 2.5 MHz 4 MHz 5 MHz
Note 1
8 MHz
Note 1
0 1 0 f
MAIN
/2
2
250 kHz 1.25 MHz 2 MHz 2.5 MHz 4 MHz
0 1 1 f
MAIN
/2
3
125 kHz 625 kHz 1 MHz 1.25 MHz 2 MHz
1 0 0 f
MAIN
/2
4
62.5 kHz 312.5 kHz 500 kHz 625 kHz 1 MHz
1 0 1 f
MAIN
/2
11
488 Hz 2.44 kHz 3.91 kHz 4.88 kHz 7.81 kHz
1 1 0 f
MAIN
/2
12
244 Hz 1.22 kHz 1.95 kHz 2.44 kHz 3.91 kHz
1 1 1 f
MAIN
/2
13
122 Hz 610 Hz 977 Hz 1.22 kHz 1.95 kHz
Note 1. The available output clock varies depending on the operating voltage range. For detail, refer to 23.4 AC
Characteristics and 24.4 AC Characteristics.
Caution 1. Change the output clock after disabling the PCLBUZ0 pin output (PCLOE0 = 0).
Caution 2. To shift to STOP mode, execute the STOP instruction after at least 1.5 clock cycles of the PCLBUZ0
pin output clock have elapsed following disabling of the PCLBUZ0 pin output (PCLOE0 = 0).
Remark f
MAIN
: Main system clock frequency
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