Renesas RL78/G15 - Oscillation Stabilization Time Counter Status Register (OSTC)

RL78/G15 CHAPTER 5 CLOCK GENERATOR
R01UH0959EJ0110 Rev.1.10 Page 138 of 765
Mar 7, 2023
5.3.4 Oscillation stabilization time counter status register (OSTC)
This register is used to indicate the count status of the X1 clock oscillation stabilization time counter.
The X1 clock oscillation stabilization time can be checked in the following case.
●
If the X1 clock starts oscillation while the high-speed on-chip oscillator clock is being used as the CPU clock.
●
If the STOP mode is entered and then released while the high-speed on-chip oscillator clock is being used as
the CPU clock with the X1 clock oscillating.
The OSTC register can be read by a 1-bit or 8-bit memory manipulation instruction.
When reset signal is generated, the STOP instruction and MSTOP (bit 7 of clock operation status control register (CSC))
= 1 clear the OSTC register to 00H.
Remark The oscillation stabilization time counter starts counting in the following cases.
 When oscillation of the X1 clock starts (EXCLK, OSCSEL = 0, 1 → MSTOP = 0)
 When the STOP mode is released
Figure 5-5. Format of Oscillation Stabilization Time Counter Status Register (OSTC)
Address: FFFA2H After reset: 00H R
Symbol 7 6 5 4 3 2 1 0
OSTC MOST8 MOST9 MOST10
MOST11 MOST13 MOST15 MOST17 MOST18
MOST8 MOST9 MOST10 MOST11 MOST13 MOST15 MOST17 MOST18 Oscillation stabilization time status
f
X
= 10 MHz f
X
= 16 MHz
0 0 0 0 0 0 0 0 (2
8
+ 16)/f
X
max.
27.2 µs max. 17.0 µs max.
1 0 0 0 0 0 0 0 (2
8
+ 16)/f
X
min.
27.2 µs min. 17.0 µs min.
1 1 0 0 0 0 0 0 (2
9
+ 16)/f
X
min.
52.8 µs min. 33.0 µs min.
1 1 1 0 0 0 0 0 (2
10
+ 16)/f
X
min.
104 µs min. 65.0 µs min.
1 1 1 1 0 0 0 0 (2
11
+ 16)/f
X
min.
206 µs min. 129 µs min.
1 1 1 1 1 0 0 0 (2
13
+ 16)/f
X
min.
820 µs min. 513 µs min.
1 1 1 1 1 1 0 0 (2
15
+ 16)/f
X
min.
3.27 ms min. 2.05 ms min.
1 1 1 1 1 1 1 0 (2
17
+ 16)/f
X
min.
13.1 ms min. 8.19 ms min.
1 1 1 1 1 1 1 1 (2
18
+ 16)/f
X
min.
26.2 ms min. 16.4 ms min.
Caution 1. After the above time has elapsed, the bits are set to 1 in order from the MOST8 bit and remain 1.