R01UH0959EJ0110 Rev.1.10 Page 19 of 765
Mar 7, 2023
CHAPTER 1 OUTLINE
1.1 Features
Low power consumption technology
V
DD
= single power supply voltage of 2.4 to 5.5 V
HALT mode
STOP mode
RL78 CPU core
CISC architecture with 3-stage pipeline
Minimum instruction execution time: Can be changed from high speed (0.0625 μs: @ 16 MHz operation with high-
speed on-chip oscillator) to low speed (1.0 μs: @ 1 MHz operation)
Address space: 1 MB
General-purpose registers: (8-bit register × 8) × 4 banks
On-chip RAM: 1 KB
Code flash memory
Code flash memory: 4 to 8 KB
Block size: 1 KB
Only write after erase is possible
On-chip debug function
Self-programming (with no boot swap function/flash shield window function)
Data flash memory
Data flash memory: 1 KB
Block size: 512 B
Unit of rewrites: 32 bits
Background operation (BGO) is not supported (instructions cannot be executed from the code flash memory while
rewriting the data flash memory)
Number of rewrites: 1,000,000 times (TYP.)
Voltage of rewrites: V
DD
= 2.4 to 5.5 V
Rev.1.10
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