RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT
R01UH0959EJ0110 Rev.1.10 Page 374 of 765
Mar 7, 2023
12.3.3 Serial mode register mn (SMRmn)
The SMRmn register is used to set an operation mode of channel n. It is also used to select an operation clock (f
MCK
),
specify whether the serial clock (f
SCK
) may be input or not, set a start trigger, the operating mode (as simplified SPI or
CSI, UART, or simplified I
2
C), and an interrupt source. This register is also used to invert the level of the receive data
only in the UART mode.
Rewriting the SMRmn register is prohibited when the register is in operation (when SEmn = 1). However, the MDmn0 bit
can be rewritten during operation.
The SMRmn register can be set by a 16-bit memory manipulation instruction.
The value of each SMRmn register is 0020H following a reset.
Figure 12-5. Format of Serial Mode Register mn (SMRmn) (1/2)
Address: F0110H, F0111H (SMR00) to F0112H, F0113H (SMR01) After reset: 0020H R/W
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMRmn
CKSm
n
CCSm
n
0 0 0 0 0
Note 1
0
SISmn
0
Note 1
1 0 0
MDmn
2
MDmn
1
MDmn
0
CKSmn Selection of operation clock (f
MCK
) of channel n
0 Operation clock CKm0 set by the SPSm register
1 Operation clock CKm1 set by the SPSm register
Operation clock (f
MCK
) is used by the edge detector. In addition, depending on the setting of the CCSmn bit and the higher
7 bits of the SDRmn register, a transfer clock (f
TCLK
) is generated.
CCSmn Selection of transfer clock (f
TCLK
) of channel n
0 Divided operation clock f
MCK
specified by the CKSmn bit
1 Clock input f
SCK
from the SCKp pin (slave transfer in simplified SPI or CSI mode)
Transfer clock f
TCLK
is used for the shift register, communication controller, output controller, interrupt controller, and error
controller. When CCSmn = 0, the division ratio of operation clock (f
MCK
) is set by the higher 7 bits of the SDRmn register.
STSmn
Note 1
Selection of start trigger source
0 Only software trigger is valid (selected for simplified SPI or CSI, UART transmission, and simplified I
2
C).
1 Valid edge of the RxDq pin (selected for UART reception)
Transfer is started when the above source is satisfied after 1 is set to the SSm register.
Note 1. The SMR01 register only.
Caution Be sure to clear bits 13 to 9, 7, 4, and 3 (or bits 13 to 6, 4, and 3 for the SMR00 register) to 0. Be sure
to set bit 5 to 1.
Remark m: Unit number (m = 0), n: Channel number (n = 0, 1), p: CSI number (p = 00, 01)
q: UART number (q = 0), r: IIC number (r = 00, 01)
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