RL78/G15 CHAPTER 5 CLOCK GENERATOR
R01UH0959EJ0110 Rev.1.10 Page 136 of 765
Mar 7, 2023
5.3.3 Clock operation status control register (CSC)
This register is used to control the operations of the high-speed system clock and high-speed on-chip oscillator clock
(except the low-speed on-chip oscillator clock).
The CSC register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to 80H.
Figure 5-4. Format of Clock Operation Status Control Register (CSC)
Address: FFFA1H After reset: 80H R/W
Symbol
□
7 6 5 4 3 2 1
□
0
CSC MSTOP 0 0 0 0 0 0 HIOSTOP
MSTOP High-speed system clock operation control
X1 oscillation mode External clock input mode Input port mode
0 X1 oscillator operating External clock from EXCLK pin is valid Input port
1 X1 oscillator stopped External clock from EXCLK pin is invalid
HIOSTOP High-speed on-chip oscillator clock operation control
0 High-speed on-chip oscillator clock operating
1 High-speed on-chip oscillator clock stopped
Caution 1. After reset release, set the clock operation mode control register (CMC) before setting the CSC
register.
Caution 2. Switch the operation mode of the X1 pin and X2 pin only when MSTOP = 1.
Caution 3. When setting MSTOP bit to 0, switch the X1 pin and X2 pin to the f
X
operation mode beforehand.
Setting the MSTOP flag is disabled in the input port mode.
Caution 4. Set the oscillation stabilization time select register (OSTS) before setting the MSTOP bit to 0 after
releasing reset. Note that if the OSTS register is being used with its default settings, the OSTS
register is not required to be set here.
Caution 5. To start X1 oscillation as set by the MSTOP bit, check the oscillation stabilization time of the X1
clock by using the oscillation stabilization time counter status register (OSTC).
Caution 6. When setting MSTOP bit to 1 in the f
X
operation mode, make sure that MCS in the CKC register is 0
beforehand.
Caution 7. In the f
X
operation mode, writing to the MSTOP flag is enabled but the stop control is not
performed.
Caution 8. Do not stop the clock selected for the CPU peripheral hardware clock (f
CLK
) with the OSC register.
Caution 9. The setting of the flags of the register to stop clock oscillation (invalidate the external clock input)
and the condition before clock oscillation is to be stopped are as Table 5-2. Before stopping the
clock oscillation, check the conditions before the clock oscillation is stopped.
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