RL78/G15 CHAPTER 3 CPU ARCHITECTURE
R01UH0959EJ0110 Rev.1.10 Page 70 of 765
Mar 7, 2023
3.3.4 Special function registers (SFRs)
Unlike a general-purpose register, each SFR has a special function.
SFRs are allocated to the FFF00H to FFFFFH area.
SFRs can be manipulated like general-purpose registers, using operation, transfer, and bit manipulation instructions. The
manipulable bit units, 1, 8, and 16, depend on the SFR type.
Each manipulation bit unit can be specified as follows.
[1-bit manipulation]
Describe as follows for the 1-bit manipulation instruction operand (sfr.bit).
When the bit name is defined: <Bit name>
When the bit name is not defined: <Register name>.<Bit number> or <Address>.<Bit number>
[8-bit manipulation]
Describe the symbol defined by the assembler for the 8-bit manipulation instruction operand (sfr). This manipulation can
also be specified with an address.
[16-bit manipulation]
Describe the symbol defined by the assembler for the 16-bit manipulation instruction operand (sfrp). When specifying an
address, describe an even address.
Table 3-5 gives a list of the SFRs. The meanings of items in the table are as follows.
[Symbol]
Symbol indicating the address of a special function register. It is a reserved word in the assembler, and is defined as an
sfr variable using the #pragma sfr directive in the compiler. When using the assembler, debugger, and simulator,
symbols can be written as an instruction operand.
[R/W]
Indicates whether the corresponding SFR can be read or written.
R/W: Read/write enable
R: Read only
W: Write only
[Manipulable bit units]
“” indicates the manipulable bit unit (1, 8, or 16). “—” indicates a bit unit for which manipulation is not possible.
[After reset]
Indicates each register status upon reset signal generation.
Caution Do not access addresses to which extended SFRs are not assigned.
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