RL78/G15 CHAPTER 14 INTERRUPT FUNCTIONS
R01UH0959EJ0110 Rev.1.10 Page 612 of 765
Mar 7, 2023
14.3.4 External interrupt rising edge enable register (EGP0), external interrupt
falling edge enable register (EGN0)
These registers specify the valid edge for INTP0 to INTP7.
The EGP0 and EGN0 registers can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears these registers to 00H.
Figure 14-5. Format of External Interrupt Rising Edge Enable Register (EGP0) and External Interrupt Falling Edge
Enable Register (EGN0)
Address: FFF38H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
EGP0 EGP07 EGP06 EGP05 EGP04 EGP03 EGP02 EGP01 EGP00
Address: FFF39H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
EGN0 EGN07 EGN06 EGN05 EGN04 EGN03 EGN02 EGN01 EGN00
EGP0n EGN0n INTPn pin valid edge selection (n = 0 to 7)
0 0 Edge detection disabled
0 1 Falling edge
1 0 Rising edge
1 1 Both rising and falling edges
Table 14-3 shows the ports corresponding to the EGP0 and EGN0 bits.
Table 14-3. Interrupt Request Signals Corresponding to EGP0 and EGN0 Bits
Detection Enable Bit Interrupt Request Signal 10-, 16-, 20-pin 8-pin
EGP00 EGN00 INTP0
EGP01 EGN01 INTP1
EGP02 EGN02 INTP2
EGP03 EGN03 INTP3
EGP04 EGN04 INTP4
EGP05 EGN05 INTP5
EGP06 EGN06 INTP6 —
EGP07 EGN07 INTP7 —
Caution When the input port pins used for the external interrupt functions are switched to the output mode,
the INTPn interrupt might be generated upon detection of a valid edge.
When switching the input port pins to the output mode, set the port mode register (PMxx) to 0 after
disabling the edge detection (by setting EGPn and EGNn to 0).
Remark 1. For edge detection port, see 2.1 Port Function.
Remark 2. n = 0 to 7
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