Renesas RL78/G15 - Lower 8 or 9 Bits of the Serial Data Register Mn (Sdrmn)

RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT
R01UH0959EJ0110 Rev.1.10 Page 369 of 765
Mar 7, 2023
12.2.2 Lower 8 or 9 bits of the serial data register mn (SDRmn)
The SDRmn is the transmit/receive data register (16 bits) of channel n.
Bits 8 to 0 (lower 9 bits) or bits 7 to 0 (lower 8 bits) function as a transmit/receive buffer register, and bits 15 to 9 are used
as a register that sets the division ratio of the operation clock (f
MCK
).
When data is received, parallel data converted by the shift register is stored in the lower 8 or 9 bits. When data is to be
transmitted, set transmit data to be transferred to the shift register to the lower 8 or 9 bits.
The data stored in the lower 8 or 9 bits of this register is as follows, depending on the setting of bits 0 and 1 (DLSmn0,
DLSmn1) of serial communication operation setting register mn (SCRmn), regardless of the output sequence of the data.
●
7-bit data length (stored in bits 0 to 6 of the SDRmn register)
●
8-bit data length (stored in bits 0 to 7 of the SDRmn register)
●
9-bit data length (stored in bits 0 to 8 of the SDRmn register)
The SDRmn register can be read or written in 16-bit units.
The lower 8 or 9 bits of the SDRmn register can be read or written
Note 1
as the following SFR, depending on the
communication mode.
●
CSIp communication … SIOp (CSIp data register)
●
UARTq reception … RXDq (UARTq receive data register)
●
UARTq transmission … TXDq (UARTq transmit data register)
●
IICr communication … SIOr (IICr data register)
The value of each SDRmn register is 0000H following a reset.
Note 1. When operation is stopped (SEmn = 0), do not rewrite SDRmn[7:0] by an 8-bit memory manipulation
instruction (SDRmn[15:9] are all cleared to 0).
Remark 1. After data is received, 0 is stored in bits 0 to 8 in bit portions that exceed the data length.
Remark 2. m: Unit number (m = 0), n: Channel number (n = 0, 1), p: CSI number (p = 00, 01)
q: UART number (q = 0), r: IIC number (r = 00, 01)