RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT
R01UH0959EJ0110 Rev.1.10 Page 455 of 765
Mar 7, 2023
12.5.7 Calculating Transfer Clock Frequency
The transfer clock frequency for simplified SPI (CSI00, CSI01) communication can be calculated by the following
expressions.
(1) Master
(
Transfer clock frequency
)
=
{
Operation clock (f
MCK
) frequency of target channel
}
÷
(
SDRmn[15: 9] + 1
)
÷ 2[Hz]
(2) Slave
(Transfer clock frequency) =
{
Frequency of serial clock (SCK) supplied by master
}
Note 1
Note 1. The permissible maximum transfer clock frequency is f
MCK
/6.
Remark The value of SDRmn[15:9] is the value of bits 15 to 9 of serial data register mn (SDRmn) (0000000B to
1111111B) and therefore is 0 to 127.
The operation clock (f
MCK
) is determined by serial clock select register m (SPSm) and bit 15 (CKSmn) of serial mode
register mn (SMRmn).
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