Renesas RL78/G15 User Manual

RL78/G15 CHAPTER 5 CLOCK GENERATOR
R01UH0959EJ0110 Rev.1.10 Page 140 of 765
Mar 7, 2023
5.3.5 Oscillation stabilization time select register (OSTS)
This register is used to select the X1 clock oscillation stabilization time at releasing of the STOP mode.
When the X1 clock is selected as the CPU clock, the operation automatically waits for the time set using the OSTS
register after the STOP mode is released. When switching the CPU clock from the high-speed on-chip oscillator clock to
the X1 clock, and when the STOP mode is entered and then released while the high-speed on-chip oscillator clock is
being used as the CPU clock with the X1 clock oscillating, use the oscillation stabilization time counter status register
(OSTC) to confirm that the oscillation stabilization time has elapsed.
Use the OSTC register to check that the oscillation stabilization time corresponding to its setting has been reached.
The OSTS register can be set by an 8-bit memory manipulation instruction.
Reset signal generation sets the OSTS register to 07H.
Figure 5-6. Format of Oscillation Stabilization Time Select Register (OSTS)
Address: FFFA3H After reset: 07H R/W
Symbol 7 6 5 4 3 2 1 0
OSTS 0 0 0 0 0 OSTS2 OSTS1 OSTS0
OSTS2 OSTS1 OSTS0 Oscillation stabilization time selection
f
X
= 10 MHz f
X
= 16 MHz
0 0 0 (2
8
+ 16)/f
X
27.2 µs 17.0 µs
0 0 1 (2
9
+ 16)/f
X
52.8 µs 33.0 µs
0 1 0 (2
10
+ 16)/f
X
104 µs 65.0 µs
0 1 1 (2
11
+ 16)/f
X
206 µs 129 µs
1 0 0 (2
13
+ 16)/f
X
820 µs 513 µs
1 0 1 (2
15
+ 16)/f
X
3.27 ms 2.05 ms
1 1 0 (2
17
+ 16)/f
X
13.1 ms 8.19 ms
1 1 1 (2
18
+ 16)/f
X
26.2 ms 16.4 ms
Caution 1. To set the STOP mode when the X1 clock is used as the CPU clock, set the OSTS register before
executing the STOP instruction.
Caution 2. Change the setting of the OSTS register before setting the MSTOP bit of the clock operation status
control register (CSC) to 0.
Caution 3. Do not change the value of the OSTS register during the X1 clock oscillation stabilization time.
Caution 4. The oscillation stabilization time counter counts up to the oscillation stabilization time set by the
OSTS register.
In the following cases, set the oscillation stabilization time of the OSTS register to the value greater
than the count value which is to be checked by the OSTC register after the oscillation starts.
 If the X1 clock starts oscillation while the high-speed on-chip oscillator clock is being used as
the CPU clock.
 If the STOP mode is entered and then released while the high-speed on-chip oscillator clock is
being used as the CPU clock with the X1 clock oscillating (note, therefore, that only the status up
to the oscillation stabilization time set by the OSTS register is set to the OSTC register after the
STOP mode is released).

Renesas RL78/G15 Specifications

General

Brand	Renesas
Model	RL78/G15
Category	Microcontrollers
Language	English