RL78/G15 CHAPTER 1 OUTLINE
R01UH0959EJ0110 Rev.1.10 Page 36 of 765
Mar 7, 2023
1.6 Outline of Functions
This outline describes the functions at the time when Peripheral I/O redirection register (PIOR) is set to 00H.
(1/2)
Item 8-pin 10-pin 16-pin 20-pin
R5F12007 R5F12008 R5F12017 R5F12018 R5F12047 R5F12048 R5F12067 R5F12068
Code flash memory 4 KB 8 KB 4 KB 8 KB 4 KB 8 KB 4 KB 8 KB
Data flash memory 1 KB
RAM 1 KB
Main system
clock
High-speed system
clock
— — X1, X2 (crystal/ceramic) oscillation: 1 to 12 MHz:
VDD = 2.4 to 5.5 V
External main system clock input (EXCLK): 1 to 16 MHz:
VDD = 2.4 to 5.5 V
High-speed on-chip
oscillator
1 to 16 MHz (VDD = 2.4 to 5.5 V)
Low-speed on-chip oscillator clock 15 kHz (TYP.)
General-purpose registers (8-bit register × 8) × 4 banks
Minimum instruction execution time 0.0625 μs (16 MHz operation)
Instruction set
Data transfer (8/16 bits)
●
Adder and subtractor/logical operation (8/16 bits)
●
Multiplication (8 bits × 8 bits)
●
Rotate, barrel shift, and bit manipulation (Set, reset, test, and Boolean operation), etc.
I/O port Total 6 8 14 18
CMOS I/O 5 7 13 17
CMOS input 1
Timer 16-bit timer 8 channels
Watchdog timer 1 channel
12-bit interval timer 1 channel
Timer output 3 channels
(PWM outputs: 2)
Note 1
3 channels
(PWM outputs: 2)
Note 1
6 channels
(PWM outputs: 4)
Note 1
8 channels
(PWM outputs: 7)
Note 1
Clock output/buzzer output 1
Up to 10 MHz (peripheral hardware clock: f
MAIN
= 10 MHz operation)
Comparator 1 channel 1 channel 1 channel 2 channels
8/10-bit resolution A/D converter 3 channels 4 channels 7 channels 11 channels
Serial interface Simplified SPI (CSI): 1 channel/simplified I
2
C:
1 channel/UART: 1 channel
Simplified SPI (CSI
Note 2
): 2 channels/simplified I
2
C:
2 channels/UART: 1 channel
I
2
C bus 1 channel
Number of
Vectored
interrupt
sources
Internal 8 10 16 19
External 6 8 8 8
Reset
Reset by RESET
pin
●
Internal reset by watchdog timer
●
Internal reset by selectable power-on-reset
●
Internal reset by illegal instruction execution
Note 3
●
Internal reset by data retention lower limit voltage
●
Internal reset by illegal-memory access
Selectable power-on-reset circuit
Detection voltage
Rising edge (V
SPOR
): 2.25 V/2.68 V/3.02 V/4.45 V (MAX.)
Falling edge (V
SPDR
): 2.20 V/2.62 V/2.96 V/4.37 V (MAX.)
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