RL78/G15 CHAPTER 14 INTERRUPT FUNCTIONS
R01UH0959EJ0110 Rev.1.10 Page 609 of 765
Mar 7, 2023
14.3.2 Interrupt mask flag registers (MK0L, MK0H, MK1L, MK1H)
The interrupt mask flags are used to enable/disable the corresponding maskable interrupt.
The MK0L, MK0H, MK1L, and MK1H registers can be set by a 1-bit or 8-bit memory manipulation instruction.
When the MK0L and MK0H registers, and the MK1L and MK1H registers are combined to form 16-bit registers MK0 and
MK1, they can be set by a 16-bit memory manipulation instruction.
Reset signal generation sets these registers to F
Remark If an instruction that writes data to this register is executed, the number of instruction execution clocks
increases by 2 clocks.
Figure 14-3. Format of Interrupt Mask Flag Registers (MK0L, MK0H, MK1L, MK1H)
Address: FFFE4H After reset: FFH R/W
Symbol
□
7
□
6
□
5
□
4
□
3
□
2
□
1
□
0
MK0L STMK0
CSIMK00
IICMK00
PMK5 PMK4 PMK3 PMK2 PMK1 PMK0 WDTIMK
Address: FFFE5H After reset: FFH R/W
Symbol
□
7
□
6
□
5
□
4
□
3
□
2
□
1
□
0
MK0H PMK7 PMK6 ADMK TMMK01 TMMK00 TMMK01H SREMK0 SRMK0
CSIMK01
IICMK01
Address: FFFE6H After reset: FFH R/W
Symbol
□
7
□
6
□
5
□
4
□
3
□
2
□
1
□
0
MK1L TMMK06 TMMK05 TMMK04 ITMK TMMK03 TMMK02 IICAMK0 TMMK03H
Address: FFFE7H After reset: FFH R/W
Symbol 7 6 5 4 3
□
2
□
1
□
0
MK1H 1 1 1 1 1 CMPMK1 CMPMK0 TMMK07
XXMKX Interrupt servicing control
0 Interrupt servicing enabled
1 Interrupt servicing disabled
Caution The available registers and bits differ depending on the product. For details about the registers and
bits available for each product, see Table 14-2. Be sure to set bits that are not available to the initial
value.
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