RL78/G15 CHAPTER 5 CLOCK GENERATOR
R01UH0959EJ0110 Rev.1.10 Page 144 of 765
Mar 7, 2023
5.3.7 Operation speed mode control register (OSMC)
This register is used to control supply of the operation clock for the 12-bit interval timer. When operating the 12-bit
interval timer, set WUTMMCK0 = 1 beforehand and do not set WUTMMCK0 = 0 until the timer is stopped.
The OSMC register can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 5-8. Format of Operation Speed Mode Control Register (OSMC)
Address: F00F3H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
OSMC 0 0 0 WUTMMCK0 0 0 0 0
WUTMMCK0 Supply of the operation clock for 12-bit interval timer
0 Stops Clock supply
1 Low-speed on-chip oscillator clock (f
IL
) supply
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