Renesas RL78/G15 - 12.7 Operation of Simplified I2 C (IIC00, IIC01) Communication

RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT
R01UH0959EJ0110 Rev.1.10 Page 483 of 765
Mar 7, 2023
12.7 Operation of Simplified I
2
C (IIC00, IIC01) Communication
This is a clocked communication function to communicate with two or more devices by using two lines: serial clock (SCL)
and serial data (SDA). This simplified I
2
C is designed for single communication with a device such as EEPROM, flash
memory, or A/D converter, and therefore, it functions only as a master.
Operate the control registers by software for setting the start and stop conditions while observing the specifications of the
I
2
C bus line.
[Data transmission/reception]
●
Master transmission, master reception (only master function with a single master)
●
ACK output function
Note 1
, ACK detection function
●
Data length of 8 bits
(When an address is transmitted, the address is specified by the higher 7 bits, and the least significant bit is used
for R/W control.)
●
Generation of start condition and stop condition for software
[Interrupt function]
●
Transfer end interrupt
[Error detection flag]
●
Overrun error
●
ACK error
*[Functions not supported by simplified I
2
C]
●
Slave transmission, slave reception
●
Multi-master function (arbitration loss detection function)
●
Wait detection functions
Note 1. When receiving the last data, ACK will not be output if 0 is written to the SOEmn (SOEm register) bit and
serial communication data output is stopped. See 12.7.3(2) Processing flow for details.
Remark m: Unit number (m = 0), n: Channel number (n = 0, 1), mn = 00, 01