Renesas RL78/G15 User Manual

RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT
R01UH0959EJ0110 Rev.1.10 Page 498 of 765
Mar 7, 2023
(2) Processing flow
Figure 12-93. Timing Chart of Data Reception
(a) When starting data reception
Shift
register mn
SCLr output
STmn
SEmn
SOEmn
SDRmn
INTIICr
TSFmn
Dummy data
(
FFH
)
D6
SDAr input
ACK
SDAr output
D5 D4 D3 D2 D1 D0D7
TXEmn = 0 / RXEmn =
1
TXEmn,
RXEmn
TXEmn
=
1
/
RXEmn
= 0
“H”
SSmn
Receive data
Shift operation
(b) When receiving last data
Shift
register mn
SCLr
output
STmn
SEmn
SOEmn
SDRmn
INTIICr
TSFmn
Dummy data (FFH)
SDAr input
ACK
SDAr output
D2
TXEmn = 0
/ RXEmn = 1
TXEmn,
RXEmn
Receive data
D
1 D0
D7
D6 D5 D4 D3 D2 D1 D0
NACK
Output by serial communication
operation is enabled.
Shift operation
Shift operation
Output by serial communication operation is stopped
.
Receive data
Dummy data (FFH)
Reception of last byte
SOmn bit
manipulation
SOmn bit
manipulation
IIC operation
stop
CKOmn bit
manipulation
Stop condition
Remark m: Unit number (m = 0), n: Channel number (n = 0, 1), r: IIC number (r = 00, 01), mn = 00, 01

Renesas RL78/G15 Specifications

General

Brand	Renesas
Model	RL78/G15
Category	Microcontrollers
Language	English