Renesas RL78/G15

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RL78/G15 CHAPTER 3 CPU ARCHITECTURE

R01UH0959EJ0110 Rev.1.10 Page 95 of 765

Mar 7, 2023

3.6 Illegal Memory Access Detection Function

The IEC60730 checks for the correct operation of the CPU and interrupts.

The illegal memory access detection function generates a reset when the specified illegal access detection space is

accessed.

The illegal access detection space is the range indicated as “NG” in Figure 3-38.

For details on the reset function, refer to CHAPTER 16 RESET FUNCTION.

Main Page

default chapter7
- Table of Contents7
Chapter 1 Outline19
- Features19
- List of Part Numbers22
- Pin Configuration (Top View)24
- 8-Pin Products24
- 10-Pin Products25
- 16-Pin Products26
- 20-Pin Products29
- Pin Identification31
- Block Diagram32
- 8-Pin Products32
- 10-Pin Products33
- 16-Pin Products34
- 20-Pin Products35
- Outline of Functions36
Chapter 2 Pin Functions38
- Port Function38
- 8-Pin Products38
- 10-Pin Products39
- 16-Pin Products40
- 20-Pin Products41
- Functions Other than Port Pins43
- Functions for each Product43
- Pins for each Product (Pins Other than Port Pins)44
- Connection of Unused Pins45
- Block Diagrams of Pins46
Chapter 3 Cpu Architecture55
- Overview55
- Memory Space56
- Internal Program Memory Space59
- Mirror Area62
- Internal Data Memory Space63
- Special Function Register (SFR) Area63
- Extended Special Function Register (2Nd SFR: 2Nd Special Function Register) Area63
- Data Memory Addressing64
- Processor Registers65
- Control Registers65
- General-Purpose Registers68
- And CS Registers69
- Special Function Registers (Sfrs)70
- Extended Special Function Registers (2Nd Sfrs: 2Nd Special Function Registers)73
- Instruction Address Addressing78
- Relative Addressing78
- Immediate Addressing79
- Register Indirect Addressing80
- Addressing for Processing Data Addresses81
- Implied Addressing81
- Register Addressing82
- Direct Addressing83
- Short Direct Addressing84
- SFR Addressing85
- Register Indirect Addressing86
- Based Addressing87
- Based Indexed Addressing91
- Stack Addressing92
- Illegal Memory Access Detection Function95
Chapter 4 Port Functions97
- Port Functions97
- Port Configuration97
- Port 098
- Port 298
- Port 498
- Port 1299
- Port13100
- Registers Controlling Port Function100
- Port Mode Registers 0, 2, 4, 12 (PM0, PM2, PM4, PM12)103
- Port Registers 0, 2, 4, 12, 13 (P0, P2, P4, P12, P13)105
- Pull-Up Resistor Option Registers 0, 2, 4, 12 (PU0, PU2, PU4, PU12)107
- Port Input Mode Registers 0, 2, 4 (POM0, POM2, POM4)109
- Port Mode Control Registers 0, 2 (PMC0, PMC2)110
- Peripheral I/O Redirection Registers 0 to 3 (PIOR0 to PIOR3)111
- Port Function Operations115
- Writing to I/O Port115
- Reading from I/O Port115
- Operations on I/O Port115
- Register Settings When Using Alternate Function116
- Basic Concept When Using Alternate Function116
- Register Settings for Alternate Function Whose Output Function Is Not Used117
- Register Setting Examples for Used Port and Alternate Functions118
- Cautions When Using Port Function127
- Cautions on 1-Bit Manipulation Instruction for Port Register N (Pn)127
- Notes on Specifying the Pin Settings128
Chapter 5 Clock Generator129
- Functions of Clock Generator129
- Configuration of Clock Generator131
- Registers Controlling Clock Generator133
- Clock Operation Mode Control Register (CMC)134
- System Clock Control Register (CKC)135
- Clock Operation Status Control Register (CSC)136
- Oscillation Stabilization Time Counter Status Register (OSTC)138
- Oscillation Stabilization Time Select Register (OSTS)140
- Peripheral Enable Register 0 (PER0)142
- Operation Speed Mode Control Register (OSMC)144
- High-Speed On-Chip Oscillator Frequency Select Register (HOCODIV)145
- High-Speed On-Chip Oscillator Trimming Register (HIOTRM)146
- System Clock Oscillator147
- X1 Oscillator (16-Pin and 20-Pin Products Only)147
- High-Speed On-Chip Oscillator150
- Low-Speed On-Chip Oscillator150
- Clock Generator Operation150
- Controlling Clock152
- Example of Setting High-Speed On-Chip Oscillator152
- Example of Setting X1 Oscillation Clock153
- CPU Clock Status Transition Diagram154
- Condition before Changing CPU Clock and Processing after Changing CPU Clock157
- Time Required for Switchover of CPU Clock and Main System Clock158
- Conditions before Clock Oscillation Is Stopped158
- Resonator and Oscillator Constants159
Chapter 6 Timer Array Unit160
- Functions of Timer Array Unit162
- Independent Channel Operation Function162
- Simultaneous Channel Operation Function165
- 8-Bit Timer Operation Function (Channels 1 and 3 Only)167
- Configuration of Timer Array Unit168
- Timer Count Register Mn (Tcrmn)173
- Timer Data Register Mn (Tdrmn)175
- Registers Controlling Timer Array Unit177
- Peripheral Enable Register 0 (PER0)178
- Timer Clock Select Register M (Tpsm)179
- Timer Mode Register Mn (Tmrmn)183
- Timer Status Register Mn (Tsrmn)189
- Timer Channel Enable Status Register M (Tem)190
- Timer Channel Start Register M (Tsm)191
- Timer Channel Stop Register M (Ttm)193
- Timer Output Enable Register M (Toem)194
- Timer Output Register M (Tom)195
- Timer Output Level Register M (Tolm)196
- Timer Output Mode Register M (Tomm)197
- Input Switch Control Register (ISC)198
- Noise Filter Enable Registers 1 (NFEN1)199
- Registers Controlling Port Functions of Pins to be Used for Timer I/O201
- Basic Rules of Timer Array Unit202
- Basic Rules of Simultaneous Channel Operation Function202
- Basic Rules of 8-Bit Timer Operation Function (Channels 1 and 3 Only)204
- Operation of Counter205
- Count Clock (F TCLK )205
- Start Timing of Counter207
- Operation of Counter208
- Channel Output (Tomn Pin) Control213
- Tomn Pin Output Circuit Configuration213
- Tomn Pin Output Setting215
- Cautions on Channel Output Operation216
- Collective Manipulation of Tomn Bit222
- Timer Interrupt and Tomn Pin Output at Count Operation Start224
- Timer Input (Timn) Control225
- Timn Input Circuit Configuration225
- Noise Filter225
- Cautions on Channel Input Operation226
- Independent Channel Operation Function of Timer Array Unit227
- Operation as Interval Timer/Square Wave Output227
- Operation as External Event Counter233
- Operation as Frequency Divider (Channels 0 and 3 Only)238
- Operation as Input Pulse Interval Measurement245
- Operation as Input Signal High-/Low-Level Width Measurement250
- Operation as Delay Counter255
- Simultaneous Channel Operation Function of Timer Array Unit260
- Operation as One-Shot Pulse Output Function260
- Operation as PWM Function270
- Operation as Multiple PWM Output Function279
- Operation as Two-Channel Input with One-Shot Pulse Output Function290
- Cautions When Using Timer Array Unit299
- Cautions When Using Timer Output299
Chapter 7 12-Bit Interval Timer300
- Functions of 12-Bit Interval Timer300
- Configuration of 12-Bit Interval Timer300
- Registers Controlling 12-Bit Interval Timer301
- Peripheral Enable Register 0 (PER0)301
- Operation Speed Mode Control Register (OSMC)302
- Interval Timer Control Register (ITMC)303
- 12-Bit Interval Timer Operation304
- 12-Bit Interval Timer Operation Timing304
- Start of Count Operation and Re-Enter to HALT/STOP Mode after Returned from HALT/STOP Mode305
Chapter 8 Clock Output/Buzzer Output Controller306
- Functions of Clock Output/Buzzer Output Controller306
- Configuration of Clock Output/Buzzer Output Controller307
- Registers Controlling Clock Output/Buzzer Output Controller307
- Clock Output Select Register 0 (CKS0)308
- Registers Controlling Port Functions of Clock Output/Buzzer Output Pin309
- Operations of Clock Output/Buzzer Output Controller310
- Operation as Output Pin310
Chapter 9 Watchdog Timer311
- Functions of Watchdog Timer311
- Configuration of Watchdog Timer312
- Register Controlling Watchdog Timer313
- Watchdog Timer Enable Register (WDTE)313
- Operation of Watchdog Timer314
- Controlling Operation of Watchdog Timer314
- Setting Time of Watchdog Timer315
Chapter 10 A/D Converter316
- Function of A/D Converter316
- Configuration of A/D Converter318
- Registers Controlling A/D Converter320
- Peripheral Enable Register 0 (PER0)321
- A/D Converter Mode Register 0 (ADM0)322
- A/D Converter Mode Register 2 (ADM2)326
- 10-Bit A/D Conversion Result Register (ADCR)327
- 8-Bit A/D Conversion Result Register (ADCRH)328
- Analog Input Channel Specification Register (ADS)329
- A/D Test Register (ADTES)330
- Registers Controlling Port Function of Analog Input Pins330
- A/D Converter Conversion Operations331
- Input Voltage and Conversion Results333
- A/D Converter Operation Modes335
- A/D Converter Setup Flowchart336
- Setting up ANI0 to ANI10 for A/D Conversion336
- Setting up the Internal Reference Voltage for A/D Conversion337
- How to Read A/D Converter Characteristics Table338
- Resolution338
- Overall Error338
- Quantization Error339
- Zero-Scale Error339
- Full-Scale Error339
- Integral Linearity Error339
- Differential Linearity Error340
- Conversion Time341
- Sampling Time341
- Notes on A/D Converter342
- Operating Current in STOP Mode342
- Input Voltage on ANI0 to ANI10 Pins342
- Conflicting Operations342
- Noise Countermeasures342
- Analog Input (Anin) Pins343
- Input Impedance of Analog Input (Anin) Pins344
- Interrupt Request Flag (ADIF)344
- Conversion Results Just after A/D Conversion Start344
- A/D Conversion Result Register (ADCR, ADCRH) Read Operation344
- 10.9.10 Internal Equivalent Circuit345
- 10.9.11 Starting the A/D Converter345
Chapter 11 Comparator346
- Comparator Functions346
- Comparator Configuration347
- Registers Controlling the Comparator349
- Peripheral Enable Register 0 (PER0)350
- Comparator Mode Setting Register (COMPMDR)351
- Comparator Filter Control Register (COMPFIR)353
- Comparator Output Control Register (COMPOCR)355
- Registers Controlling Port Functions of Comparator I/O Pins356
- Comparator N Operation (N = 0, 1)357
- Comparator N Digital Filter Operation (N = 0, 1)358
- Comparator N Interrupt Operation (N = 0, 1)358
- Comparator N Output (N = 0, 1)358
- Comparator Setting Flowcharts359
- Enabling Comparator Operation (in the Case of CMP0)360
- Disabling Comparator Operation (in the Case of CMP0)361
Chapter 12 Serial Array Unit362
- Functions of Serial Array Unit363
- Simplified SPI (CSI00, CSI01)363
- Uart (Uart0)364
- Simplified I C (IIC00, IIC01)365
- Configuration of Serial Array Unit366
- Shift Register368
- Lower 8 or 9 Bits of the Serial Data Register Mn (Sdrmn)369
- Registers to Control the Serial Array Unit371
- Peripheral Enable Register 0 (PER0)372
- Serial Clock Select Register M (Spsm)373
- Serial Mode Register Mn (Smrmn)374
- Serial Communication Operation Setting Register Mn (Scrmn)376
- Serial Data Register Mn (Sdrmn)379
- Serial Flag Clear Trigger Register Mn (Sirmn)381
- Serial Status Register Mn (Ssrmn)382
- Serial Channel Start Register M (Ssm)384
- Serial Channel Stop Register M (Stm)385
- Serial Channel Enable Status Register M (Sem)386
- Serial Output Enable Register M (Soem)387
- Serial Output Register M (Som)388
- Serial Output Level Register M (Solm)389
- Input Switch Control Register (ISC)391
- Noise Filter Enable Register 0 (NFEN0)392
- 12.3.16 Registers Controlling Port Functions of Serial Input/Output Pins393
- Operation Stop Mode394
- Stopping the Operation by Units394
- Stopping the Operation by Channels395
- Operation of Simplified SPI (CSI00, CSI01) Communication397
- Master Transmission399
- Master Reception408
- Master Transmission/Reception418
- Slave Transmission428
- Slave Reception437
- Slave Transmission/Reception444
- Calculating Transfer Clock Frequency455
- Procedure for Processing Errors that Occurred During Simplified SPI (CSI00, CSI01) Communication457
- Operation of UART (UART0) Communication458
- UART Transmission460
- UART Reception470
- Calculating Baud Rate477
- Procedure for Processing Errors that Occurred During UART (UART0) Communication482
- Operation of Simplified I C (IIC00, IIC01) Communication483
- Address Field Transmission485
- Data Transmission491
- Data Reception495
- Stop Condition Generation500
- Calculating Transfer Rate501
- Procedure for Processing Errors that Occurred During Simplified I504
- C (Iic00, Iic01)504
- Communication504
Chapter 13 Serial Interface Iica505
- Functions of Serial Interface IICA505
- Configuration of Serial Interface IICA508
- Registers Controlling Serial Interface IICA512
- Peripheral Enable Register 0 (PER0)513
- IICA Control Register 00 (IICCTL00)514
- IICA Status Register 0 (IICS0)518
- IICA Flag Register 0 (IICF0)521
- IICA Control Register 01 (IICCTL01)523
- IICA Low-Level Width Setting Register 0 (IICWL0)526
- IICA High-Level Width Setting Register 0 (IICWH0)526
- Registers Controlling Port Functions of IICA Serial Input/Output Pins527
- I 2 C Bus Mode Functions528
- Pin Configuration528
- Setting Transfer Clock by Using IICWL0 and IICWH0 Registers529
- I 2 C Bus Definitions and Control Methods531
- Start Condition532
- Address533
- Transfer Direction Specification534
- Acknowledge (ACK)534
- Stop Condition536
- Clock Stretching537
- Releasing Clock Stretching539
- Interrupt Request (INTIICA0) Generation Timing and Clock Stretching Control540
- Address Match Detection Method541
- 13.5.10 Error Detection541
- 13.5.11 Extension Code542
- 13.5.12 Arbitration543
- 13.5.13 Wakeup Function545
- 13.5.14 Communication Reservation548
- 13.5.15 Cautions552
- 13.5.16 Communication Operations554
- C Interrupt Request (INTIICA0) Generation Timing564
- Timing Charts585
Chapter 14 Interrupt Functions600
- Interrupt Function Types600
- Interrupt Sources and Configuration600
- Registers Controlling Interrupt Functions605
- Interrupt Request Flag Registers (IF0L, IF0H, IF1L, IF1H)607
- Interrupt Mask Flag Registers (MK0L, MK0H, MK1L, MK1H)609
- Priority Specification Flag Registers (PR00L, PR00H, PR01L, PR01H, PR10L, PR10H, PR11L, PR11H)610
- External Interrupt Rising Edge Enable Register (EGP0), External Interrupt Falling Edge Enable Register (EGN0)612
- Program Status Word (PSW)613
- Interrupt Servicing Operations614
- Maskable Interrupt Request Acknowledgment614
- Software Interrupt Request Acknowledgment617
- Multiple Interrupt Servicing617
- Interrupt Request Pending622
Chapter 15 Standby Function624
- Overview624
- Registers Controlling Standby Function625
- Standby Function Operation625
- HALT Mode625
- STOP Mode629
Chapter 16 Reset Function635
- Timing of Reset Operation637
- States of Operation During Reset Periods639
- Register for Confirming Reset Source641
- Reset Control Flag Register (RESF)641
Chapter 17 Selectable Power-On-Reset Circuit644
- Functions of Selectable Power-On-Reset Circuit644
- Configuration of Selectable Power-On-Reset Circuit645
- Operation of Selectable Power-On-Reset Circuit646
- Cautions for Selectable Power-On-Reset Circuit647
Chapter 18 Option Byte648
- Functions of Option Bytes648
- User Option Byte (000C0H to 000C2H)648
- On-Chip Debug Option Byte (000C3H)648
- Format of User Option Byte649
- Format of On-Chip Debug Option Byte652
- Setting of Option Byte653
Chapter 19 Flash Memory654
- Serial Programming Using Flash Memory Programmer656
- Programming Environment658
- Communication Mode658
- Writing to Flash Memory by Using External Device (that Incorporates UART)660
- Programming Environment660
- Communication Mode661
- Connection of Pins on Board662
- P40/TOOL0 Pin662
- RESET ¯¯¯¯¯¯ Pin663
- Port Pins663
- X1 and X2 Pins (16-Pin and 20-Pin Products)663
- Power Supply664
- Serial Programming Method665
- Serial Programming Procedure665
- Flash Memory Programming Mode666
- Selecting Communication Mode667
- Communication Commands667
- Processing Time for each Command When PG-FP5 Is in Use (Reference Values)668
- Self-Programming669
- Registers Controlling Self-Programming669
- Flash Address Pointer Registers H and L (FLAPH, FLAPL)670
- Flash End Address Specification Registers H and L (FLSEDH, FLSEDL)671
- Flash Write Buffer Registers HH, HL, LH, and LL (FLWHH, FLWHL, FLWLH, FLWLL)673
- Flash Programming Mode Control Register (FLPMC)674
- Flash Memory Sequencer Initial Setting Register (FSSET)675
- Flash Memory Sequencer Control Register (FSSQ)676
- Flash Memory Sequencer Status Registers H and L (FSASTH, FSASTL)677
- Procedure for Executing Self-Programming of Code/Data Flash Memory678
- Notes on Self-Programming681
- Data Flash682
- Data Flash Overview682
- Procedure for Accessing Data Flash Memory682
Chapter 20 On-Chip Debug Function683
- Connecting E2, E2 Lite On-Chip Debugging Emulator683
- Connecting External Device (that Incorporates UART)685
- On-Chip Debug Security ID686
- Securing of User Resources687
Chapter 21 Bcd Correction Circuit689
- BCD Correction Circuit Function689
- Registers Used by BCD Correction Circuit689
- BCD Correction Result Register (BCDADJ)689
- BCD Correction Circuit Operation690
Chapter 22 Instruction Set692
- Conventions Used in Operation List692
- Operand Identifiers and Specification Methods692
- Description of Operation Column694
- Description of Flag Operation Column695
- PREFIX Instruction695
- Operation List696
Chapter 23 Electrical Specifications709
- Absolute Maximum Ratings710
- Oscillator Characteristics711
- X1 Oscillator Characteristics711
- On-Chip Oscillator Characteristics711
- DC Characteristics712
- Pin Characteristics712
- Supply Current Characteristics714
- AC Characteristics716
- Serial Interface Characteristics719
- Serial Array Unit719
- Serial Interface IICA724
- Analog Characteristics725
- A/D Converter Characteristics725
- Comparator Characteristics726
- Internal Reference Voltage Characteristics726
- SPOR Circuit Characteristics727
- Power Supply Voltage Rising Slope Characteristics727
- RAM Data Retention Characteristics728
- Flash Memory Programming Characteristics729
- Dedicated Flash Memory Programmer Communication (UART)729
- 23.10 Timing of Entry to Flash Memory Programming Mode730
Chapter 24 Electrical Specifications (T +125°C)731
- CHAPTER 24 ELECTRICAL SPECIFICATIONS (T = −40 to +105°C, T = −40 to +125°C)731
- Absolute Maximum Ratings732
- Oscillator Characteristics733
- X1 Oscillator Characteristics733
- On-Chip Oscillator Characteristics733
- DC Characteristics734
- Pin Characteristics734
- Supply Current Characteristics736
- AC Characteristics738
- Serial Interface Characteristics741
- Serial Array Unit741
- Serial Interface IICA746
- Analog Characteristics747
- A/D Converter Characteristics747
- Comparator Characteristics748
- Internal Reference Voltage Characteristics748
- SPOR Circuit Characteristics749
- Power Supply Voltage Rising Slope Characteristics749
- RAM Data Retention Characteristics750
- Flash Memory Programming Characteristics751
- Dedicated Flash Memory Programmer Communication (UART)751
- 24.10 Timing of Entry to Flash Memory Programming Mode752
Chapter 25 Package Drawings753
- 8-Pin Products753
- 10-Pin Products754
- 16-Pin Products755
- 20-Pin Products757
Appendix A Revision History758
- Major Revisions in this Edition758
- Revision History of Preceding Editions760

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