RL78/G15 CHAPTER 3 CPU ARCHITECTURE
R01UH0959EJ0110 Rev.1.10 Page 94 of 765
Mar 7, 2023
Figure 3-36. Example of Interrupt, BRK
Instruction code
OP-code
Memory
F0000H
• Stack addressing is specified <1>. In response to a BRK
instruction or acceptance of an interrupt, the value of the program
counter (PC) changes to indicate the address of the next
instruction.
• The values of the PSW, PC bits 19 to 16, 15 to 8, and 7 to 0 are
stored in addresses SP – 1, SP – 2, SP – 3, and SP – 4,
respectively <2>.
• The value of the SP <3> is decreased by 4.
PC19 to PC16
SP – 1
SP – 2
SP – 3
SP – 4
SP
PC15 to PC8
Stack
area
SP
<3>
<1>
PC7 to PC0
PSW
Interrupt
or
PSW
PC
<2>
<2>
Figure 3-37. Example of RETI, RETB
Instruction code
OP-code
Memory
F0000H
• Stack addressing is specified <1
>.
• The contents of addresses SP, SP + 1, SP + 2, and SP + 3 are
stored in PC bits 7 to 0, 15 to 8, 19 to 16, and the PSW,
respectively <2>.
•
The value of SP <3> is increased by 4.
(SP
+ 2)
SP + 3
SP + 2
SP
+ 1
SP
RETI,
<
1>
SP
(SP + 1)
Stack
area
SP
<3>
PC
<1>
(SP)
(SP + 3)
<2>
SP + 4
RETB
PSW
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