RL78/G15 CHAPTER 14 INTERRUPT FUNCTIONS
R01UH0959EJ0110 Rev.1.10 Page 607 of 765
Mar 7, 2023
14.3.1 Interrupt request flag registers (IF0L, IF0H, IF1L, IF1H)
The interrupt request flags are set to 1 when the corresponding interrupt request is generated or an instruction is
executed. They are cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request or upon
reset signal generation.
When an interrupt is acknowledged, the interrupt request flag is automatically cleared and then the interrupt routine is
entered.
The IF0L, IF0H, IF1L, and IF1H registers can be set by a 1-bit or 8-bit memory manipulation instruction. When the IF0L
and IF0H registers, and the IF1L and IF1H registers are combined to form 16-bit registers IF0 and IF1, they can be set
by a 16-bit memory manipulation instruction.
Reset signal generation clears these registers to 00H.
Remark If an instruction that writes data to this register is executed, the number of instruction execution clocks
increases by 2 clocks
Figure 14-2. Format of Interrupt Request Flag Registers (IF0L, IF0H, IF1L, IF1H)
Address: FFFE0H After reset: 00H R/W
Symbol
□
7
□
6
□
5
□
4
□
3
□
2
□
1
□
0
IF0L STIF0
CSIIF00
IICIF00
PIF5 PIF4 PIF3 PIF2 PIF1 PIF0 WDTIIF
Address: FFFE1H After reset: 00H R/W
Symbol
□
7
□
6
□
5
□
4
□
3
□
2
□
1
□
0
IF0H PIF7 PIF6 ADIF TMIF01 TMIF00 TMIF01H SREIF0 SRIF0
CSIIF01
IICIF01
Address: FFFE2H After reset: 00H R/W
Symbol
□
7
□
6
□
5
□
4
□
3
□
2
□
1
□
0
IF1L TMIF06 TMIF05 TMIF04 ITIF TMIF03 TMIF02 IICAIF0 TMIF03H
Address: FFFE3H After reset: 00H R/W
Symbol 7 6 5 4 3
□
2
□
1
□
0
IF1H 0 0 0 0 0 CMPIF1 CMPIF0 TMIF07
XXIFX Interrupt request flag
0 No interrupt request signal is generated
1 An interrupt request signal is generated and the interrupt is requested.
Caution 1. The available registers and bits differ depending on the product.
For details about the registers and bits available for each product, see Table 14-2. Be sure to set
bits that are not available to the initial value.
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