RL78/G15 CHAPTER 6 TIMER ARRAY UNIT
R01UH0959EJ0110 Rev.1.10 Page 178 of 765
Mar 7, 2023
6.3.1 Peripheral enable register 0 (PER0)
This register is used to enable or disable supplying the clock to the peripheral hardware. Clock supply to a hardware
macro that is not used is stopped in order to reduce the power consumption and noise.
When the timer array unit 0 is used, be sure to set bit 0 (TAU0EN) of this register to 1.
The PER0 register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 6-9. Format of Peripheral Enable Register 0 (PER0)
Address: F00F0H After reset: 00H R/W
Symbol
□
7
□
6
□
5
□
4
□
3
□
2
□
1
□
0
PER0 TMKAEN CMPEN ADCEN IICA0EN 0 SAU0EN 0 TAU0EN
TAU0EN Control of timer array unit 0 input clock
0 Stops supply of input clock.
●
SFR used by the timer array unit 0 cannot be written.
●
The timer array unit 0 is in the reset status.
1 Supplies input clock.
●
SFR used by the timer array unit 0 can be read/written.
Caution 1. When setting the timer array unit, be sure to set the following registers first while the TAUmEN bit
is set to 1. If TAUmEN = 0, the values of the registers which control the timer array unit are cleared
to their initial values and writing to them is ignored (except for input switch control register (ISC),
noise filter enable register 1 (NFEN1), port mode control register 0, 2 (PMC0, PMC2), port mode
register 0, 2, 4, 12 (PM0, PM2, PM4, PM12), and port register 0, 2, 4, 12, 13 (P0, P2, P4, P12, P13)).
Timer clock select register m (TPSm)
Timer mode register mn (TMRmn)
Timer status register mn (TSRmn)
Timer channel enable status register m (TEm)
Timer channel start register m (TSm)
Timer channel stop register m (TTm)
Timer output enable register m (TOEm)
Timer output register m (TOm)
Timer output level register m (TOLm)
Timer output mode register m (TOMm)
Caution 2. Be sure to clear the following bits to 0.
Bits 1, 3
To Next Page
Loading...
Need help?
General
