RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT
R01UH0959EJ0110 Rev.1.10 Page 457 of 765
Mar 7, 2023
Note 1. When changing the clock selected for f
CLK
(by changing the system clock control register (CKC) value), do so
after having stopped (serial channel stop register m (STm) = 000FH) the operation of the serial array unit
(SAU).
Remark 1. X: Don’t care
Remark 2. m: Unit number (m = 0), n: Channel number (n = 0, 1), mn = 00, 01
12.5.8 Procedure for Processing Errors that Occurred During Simplified SPI
(CSI00, CSI01) Communication
The procedure for processing errors that occurred during simplified SPI (CSI00, CSI01) communication is described in
Figure 12-67.
Figure 12-67. Processing Procedure in Case of Overrun Error
Software Manipulation State of the Hardware Remark
Reads serial data register mn (SDRmn).
The BFFmn bit of the SSRmn register
is set to 0 and channel n is enabled to
receive data.
This is to prevent an overrun error if the next
reception is completed during error
processing.
Reads serial status register mn
(SSRmn).
The error type is identified and the read value
is used to clear the error flag.
Writes 1 to serial flag clear trigger
register mn (SIRmn).
The error flag is cleared.
The error only during reading can be cleared,
by writing the value read from the SSRmn
register to the SIRmn register without
modification.
Remark m: Unit number (m = 0), n: Channel number (n = 0, 1), mn = 00, 01
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