RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT
R01UH0959EJ0110 Rev.1.10 Page 376 of 765
Mar 7, 2023
12.3.4 Serial communication operation setting register mn (SCRmn)
The SCRmn is a communication operation setting register of channel n. It is used to set a data transmission/reception
mode, phase of data and clock, whether an error signal is to be masked or not, parity bit, start bit, stop bit, and data
length.
Rewriting the SCRmn register is prohibited when the register is in operation (when SEmn = 1).
The SCRmn register can be set by a 16-bit memory manipulation instruction.
The value of each SCRmn register is 0087H following a reset.
Figure 12-6. Format of Serial Communication Operation Setting Register mn (SCRmn) (1/2)
Address: F0118H, F0119H (SCR00) to F011AH, F011BH (SCR01) After reset: 0087H R/W
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCRmn
RXEm
n
DAPm
n
CKPm
n
0
EOCm
n
PTCm
n1
PTCm
n0
DIRmn
0
1
Note 1
0
0 1
1
0
TXEmn RXEmn Setting of operation mode of channel n
0 0 Disable communication.
0 1 Reception only
1 0 Transmission only
1 1 Transmission/reception
DAPmn CKPmn Selection of data and clock phase in simplified SPI (CSI) mode Type
0 0 1
0 1 2
1 0 3
1 1 4
Be sure to set DAPmn, CKPmn = 0, 0 in the UART mode and simplified I
2
C mode.
Note 1. The SCR00 register only.
Caution Be sure to clear bits 3, 6, and 11 to 0 (Also clear bit 5 of the SCR01 register to 0). Be sure to set bit 2
to 1.
Remark m: Unit number (m = 0), n: Channel number (n = 0, 1), p: CSI number (p = 00, 01)
D
7 D6
D5 D4 D3 D2 D1 D0
SCKp
SOp
SIp input timing
D7 D6 D5 D4 D3 D2 D1 D0
SCKp
SOp
SIp input timing
D7 D6 D5 D4 D3 D2 D1 D0
SCKp
SOp
SIp input timing
D7
D6 D
5 D4 D3 D2 D1
D0
SCKp
SOp
SIp input timing
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