Renesas RL78/G15

RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT
R01UH0959EJ0110 Rev.1.10 Page 377 of 765
Mar 7, 2023
Figure 12-6. Format of Serial Communication Operation Setting Register mn (SCRmn) (2/2)
Address: F0118H, F0119H (SCR00) to F011AH, F011BH (SCR01) After reset: 0087H R/W
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCRmn
TXEmn
RXEm
n
DAPm
n
CKPm
n
0
EOCm
n
PTCm
n1
PTCm
n0
DIRmn
0
SLCmn
1
Note 1
SLCmn
0
0 1
DLSmn
1
DLSmn
0
EOCmn Mask control of error interrupt signal (INTSREx (x = 0 to 3))
0 Disables generation of error interrupt INTSREx (INTSRx is generated).
1 Enables generation of error interrupt INTSREx (INTSRx is not generated if an error occurs).
Set EOCmn = 0 in the simplified SPI (CSI) mode, simplified I
2
C mode, and during UART transmission.
Note 2
PTCmn
1
PTCmn
0
Setting of parity bit in UART mode
Transmission Reception
0 0 Does not output the parity bit. Receives without parity
0 1 Outputs 0 parity.
Note 3
No parity judgment
1 0 Outputs even parity. Judged as even parity.
1 1 Outputs odd parity. Judges as odd parity.
Be sure to set PTCmn1, PTCmn0 = 0, 0 in the simplified SPI (CSI) mode and simplified I
2
C mode.
DIRmn Selection of data transfer sequence in simplified SPI (CSI) and UART modes
0 Inputs/outputs data with MSB first.
1 Inputs/outputs data with LSB first.
Be sure to clear DIRmn = 0 in the simplified I
2
C mode.
SLCmn
1
Note 1
SLCmn
0
Setting of stop bit in UART mode
0 0 No stop bit
0 1 Stop bit length = 1 bit
1 0 Stop bit length = 2 bits (mn = 00 only)
1 1 Setting prohibited
When the transfer end interrupt is selected, the interrupt is generated when all stop bits have been completely transferred.
Set 1 bit (SLCmn1, SLCmn0 = 0, 1) during UART reception and in the simplified I
2
C mode.
Set no stop bit (SLCmn1, SLCmn0 = 0, 0) in the simplified SPI (CSI) mode.
Set 1 bit (SLCmn1, SLCmn0 = 0, 1) or 2 bits (SLCmn1, SLCmn0 = 1, 0) during UART transmission.
DLSmn
1
DLSmn
0
Setting of data length in simplified SPI (CSI) and UART modes
0 1 9-bit data length (stored in bits 0 to 8 of the SDRmn register) (settable in UART mode only)
1 0 7-bit data length (stored in bits 0 to 6 of the SDRmn register)
1 1 8-bit data length (stored in bits 0 to 7 of the SDRmn register)
Other than above Setting prohibited
Be sure to set DLSmn1, DLSmn0 = 1, 1 in the simplified I
2
C mode.
Note 1. The SCR00 register only.