RL78/G15 CHAPTER 11 COMPARATOR
R01UH0959EJ0110 Rev.1.10 Page 355 of 765
Mar 7, 2023
11.3.4 Comparator Output Control Register (COMPOCR)
This register selects the comparator response speed, controls the VCOUTn output, and enables or disables the interrupt
request signal.
Remark n = 0, 1
The COMPOCR register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 11-5. Format of Comparator Output Control Register (COMPOCR)
Address: FFF62H After reset: 00H R/W
Symbol
□
7
□
6
□
5
□
4 3
□
2
□
1
□
0
COMPOCR SPDMD C1OP C1OE C1IE 0 C0OP C0OE C0IE
SPDMD
Note 1
Comparator speed selection
0 Low-speed mode
1 High-speed mode
C1OP VCOUT1 output polarity selection
0 Non-inverted comparator 1 output is output from the VCOUT1 pin.
1 Inverted comparator 1 output is output from the VCOUT1 pin.
C1OE VCOUT1 pin output enable/disable
0 Comparator 1 VCOUT1 pin output disabled
1 Comparator 1 VCOUT1 pin output enabled
C1IE Comparator 1 interrupt request enable/disable
0 Comparator 1 interrupt request disabled
1 Comparator 1 interrupt request enabled
C0OP VCOUT0 output polarity selection
0 Non-inverted comparator 0 output is output from the VCOUT0 pin.
1 Inverted comparator 0 output is output from the VCOUT0 pin.
C0OE VCOUT0 pin output enable/disable
0 Comparator 0 VCOUT0 pin output disabled
1 Comparator 0 VCOUT0 pin output enabled
C0IE Comparator 0 interrupt request enable/disable
0 Comparator 0 interrupt request disabled
1 Comparator 0 interrupt request enabled
Note 1. When rewriting the SPDMD bit, be sure to clear the CnENB bit (n = 0, 1) in the COMPMDR register to 0 in
advance.
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