RL78/G15 CHAPTER 11 COMPARATOR
R01UH0959EJ0110 Rev.1.10 Page 354 of 765
Mar 7, 2023
Note 3. To use the comparator in STOP mode, disable the digital filter (C1FCK1 and C1FCK0 = 00B).
Note 4. If the C0EDG, C0EPO, and C0FCK1 or C0FCK0 bits are changed while operation of the comparator 0 is
enabled, a comparator detection 0 interrupt (INTCMP0) may be generated. Change these bits only after
clearing the C0IE bit in the COMPOCR register to 0 to disable an interrupt request.
Also, be sure to clear bit 1 (CMPIF0) in the interrupt request flag register 1H (IF1H) to 0 after changing these
bits.
Note 5. If the value of the C0FCK1 or C0FCK0 bit is changed, a wait period of four cycles of the sampling clock is
required to update the digital filter. To use the comparator detection 0 interrupt (INTCMP0), set the C0IE bit in
the COMPOCR register to 1 after this wait period.
Note 6. To use the comparator in STOP mode, disable the digital filter (C0FCK1 and C0FCK0 = 00B).
Remark ×: Don’t care
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