RL78/G15 CHAPTER 14 INTERRUPT FUNCTIONS
R01UH0959EJ0110 Rev.1.10 Page 614 of 765
Mar 7, 2023
14.4 Interrupt Servicing Operations
14.4.1 Maskable interrupt request acknowledgment
A maskable interrupt request becomes acknowledgeable when the interrupt request flag is set to 1 and the mask (MK)
flag corresponding to that interrupt request is cleared to 0. A vectored interrupt request is acknowledged if interrupts are
in the interrupt enabled state (when the IE flag is set to 1). However, a low-priority interrupt request is not acknowledged
during servicing of a higher priority interrupt request.
The times from generation of a maskable interrupt request until vectored interrupt servicing is performed are listed in
Table 14-4.
For the interrupt request acknowledgment timing, see Figure 14-8 and Figure 14-9.
Table 14-4. Time from Generation of Maskable Interrupt until Servicing
Minimum Time Maximum Time
Note 1
Servicing time 9 clocks 16 clocks
Note 1. Maximum time does not apply when an instruction from the internal RAM area is executed.
Remark 1 clock: 1/f
CLK
(f
CLK
: CPU clock)
If two or more maskable interrupt requests are generated simultaneously, the request with a higher priority level specified
in the priority specification flag is acknowledged first. If two or more interrupts requests have the same priority level, the
request with the highest default priority is acknowledged first.
An interrupt request that is held pending is acknowledged when it becomes acknowledgeable.
Figure 14-7 shows the interrupt request acknowledgment algorithm.
If a maskable interrupt request is acknowledged, the contents are saved into the stacks in the order of PSW, then PC,
the IE flag is reset (0), and the contents of the priority specification flag corresponding to the acknowledged interrupt are
transferred to the ISP1 and ISP0 flags. The vector table data determined for each interrupt request is the loaded into the
PC and branched.
Returning from an interrupt is possible by using the RETI instruction.
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