RL78/G15 CHAPTER 6 TIMER ARRAY UNIT
R01UH0959EJ0110 Rev.1.10 Page 196 of 765
Mar 7, 2023
6.3.10 Timer output level register m (TOLm)
The TOLm register is a register that controls the timer output level of each channel.
The setting of the inverted output of channel n by this register is reflected at the timing of set or reset of the timer output
signal while the timer output is enabled (TOEmn = 1) in the simultaneous channel operation function (TOMmn = 1). In the
master channel output mode (TOMmn = 0), this register setting is invalid.
The TOLm register can be set by a 16-bit memory manipulation instruction.
The lower 8 bits of the TOLm register can be set with an 8-bit memory manipulation instruction with TOLmL.
Reset signal generation clears this register to 0000H.
Figure 6-18. Format of Timer Output Level register m (TOLm)
Address: F01BCH, F01BDH (TOL0) After reset: 0000H R/W
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TOLm 0 0 0 0 0 0 0 0
0
TOLmn Control of timer output level of channel n
0 Positive logic output (active-high)
1 Negative logic output (active-low)
Caution Be sure to clear bits 15 to 8, and 0 to 0.
Remark 1. If the value of this register is rewritten during timer operation, the timer output logic is inverted when the
timer output signal changes next, instead of immediately after the register value is rewritten.
Remark 2. m: Unit number (m = 0), n: Channel number (n = 0 to 7)
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