RL78/G15 CHAPTER 16 RESET FUNCTION
R01UH0959EJ0110 Rev.1.10 Page 637 of 765
Mar 7, 2023
16.1 Timing of Reset Operation
This LSI is reset by input of the low level on the RESET
¯¯¯¯¯¯
pin and released from the reset state by input of the high level
on the RESET
¯¯¯¯¯¯
pin. After reset processing, execution of the program with the high-speed on-chip oscillator clock as the
operating clock starts.
Figure 16-2. Timing of Reset by RESET
¯¯¯¯¯¯
Input
Hi-Z
Note 3
Normal operation
CPU status
Normal operation (high-speed on-chip oscillator clock)
______
RESET
________________
Internal reset signal
Port pin
Wait for oscillation
accuracy stabilization
Delay
High-speed on-chip
oscillator clock
Reset period
(oscillation stop)
High-speed system clock
(when X1 oscillation is
selected)
Note 1
Starting X1 oscillation is specified by software.
Reset processing for release from the external reset
state: 500 μs (typ.)
Note 2
Note 1. 16-pin and 20-pin products only.
Note 2. After power is supplied, an SPOR reset processing time of 3.01 ms (MAX.) is required before reset
processing starts after release of the external reset.
Note 3. Status of port pin P40 is as follows.
High-impedance during external reset period or reset period by the data retention power supply voltage
High level after receiving a reset (connected to the internal pull-up resistor)
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