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Renesas RL78/G15

Renesas RL78/G15
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RL78/G15 CHAPTER 21 BCD CORRECTION CIRCUIT
R01UH0959EJ0110 Rev.1.10 Page 689 of 765
Mar 7, 2023
CHAPTER 21 BCD CORRECTION CIRCUIT
21.1 BCD Correction Circuit Function
The result of addition/subtraction of the BCD (binary-coded decimal) code and BCD code can be obtained as BCD code
with this circuit.
The decimal correction operation result is obtained by performing addition/subtraction having the A register as the
operand and then adding/subtracting the BCD correction result register (BCDADJ).
21.2 Registers Used by BCD Correction Circuit
The BCD correction circuit uses the following registers.
BCD correction result register (BCDADJ)
21.2.1 BCD correction result register (BCDADJ)
The BCDADJ register stores correction values for obtaining the add/subtract result as BCD code through add/subtract
instructions using the A register as the operand.
The value read from the BCDADJ register varies depending on the value of the A register when it is read and those of
the CY and AC flags.
The BCDADJ register is read by an 8-bit memory manipulation instruction.
Reset input sets this register to undefined.
Figure 21-1. Format of BCD Correction Result Register (BCDADJ)
Address: F00FEH After reset: undefined R
Symbol 7 6 5 4 3 2 1 0
BCDADJ

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