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Renesas RL78/G15 User Manual

Renesas RL78/G15
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RL78/G15 CHAPTER 14 INTERRUPT FUNCTIONS
R01UH0959EJ0110 Rev.1.10 Page 608 of 765
Mar 7, 2023
Caution 2. When manipulating a flag of the interrupt request flag register, use a 1-bit memory manipulation
instruction (CLR1). When describing in C language, use a bit manipulation instruction such as
IF0L.0 = 0;or _asm(clr1 IF0L.0”);” because the compiled assembler must be a 1-bit memory
manipulation instruction (CLR1).
If a program is described in C language using an 8-bit memory manipulation instruction such as
IF0L &= 0xfe;and compiled, it becomes the assembler of three instructions.
mov a, IF0L
and a, #0FEH
mov IF0L, a
In this case, even if the request flag of the another bit of the same interrupt request flag register
(IF0L) is set to 1 at the timing between mov a, IF0Land mov IF0L, a, the flag is cleared to 0 at
mov IF0L, a. Therefore, care must be exercised when using an 8-bit memory manipulation
instruction in C language.

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Renesas RL78/G15 Specifications

General IconGeneral
BrandRenesas
ModelRL78/G15
CategoryMicrocontrollers
LanguageEnglish

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