RL78/G15 CHAPTER 5 CLOCK GENERATOR
R01UH0959EJ0110 Rev.1.10 Page 143 of 765
Mar 7, 2023
Figure 5-7. Format of Peripheral Enable Register 0 (PER0) (2/2)
Address: F00F0H After reset: 00H R/W
Symbol
□
7
□
6
□
5
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4 3
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2 1
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0
PER0 TMKAEN
Note 1
CMPEN
Note 1
ADCEN IICA0EN
Note 1
0 SAU0EN 0 TAU0EN
IICA0EN Control of serial interface IICA input clock supply
0 Stops input clock supply.
●
SFR used by the serial interface IICA cannot be written.
●
The serial interface IICA is in the reset status.
1 Enables input clock supply.
●
SFR used by the serial interface IICA can be read and written.
SAU0EN Control of serial array unit input clock supply
0 Stops input clock supply.
●
SFR used by the serial array unit cannot be written.
●
The serial array unit is in the reset status.
1 Enables input clock supply.
●
SFR used by the serial array unit can be read and written.
TAU0EN Control of timer array unit input clock supply
0 Stops input clock supply.
●
SFR used by the timer array unit cannot be written.
●
The timer array unit is in the reset status.
1 Enables input clock supply.
●
SFR used by the timer array unit can be read and written.
Note 1. 16-pin and 20-pin products only.
Caution 1. Be sure to clear bits 1 and 3 to 0.
Caution 2. Be sure to clear the following bits to 0.
8-pin and 10-pin products: bits 1, 3, 4, 6, 7
16-pin and 20-pin products: bits 1, 3
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