RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA
R01UH0959EJ0110 Rev.1.10 Page 530 of 765
Mar 7, 2023
(2) Setting IICWL0 and IICWH0 registers on slave side
(The fractional parts of all setting values are rounded up.)
●
In fast mode
IICWL0 = 1.3 s × f
IICWH0 =
(
1.2 s t
t
)
× f
●
In normal mode
IICWL0 = 4.7 s × f
IICWH0 =
(
5.3 s t
t
)
× f
Caution When setting the transfer clock, take care with the minimum operation frequency of f
CLK
. The
minimum operation frequency of f
CLK
for serial interface IICA is determined according to the mode.
Fast mode: f
CLK
= 3.5 MHz (min.)
Normal mode: f
CLK
= 1 MHz (min.)
Remark 1. Calculate the rise time (t
R
) and fall time (t
F
) of the SDAA0 and SCLA0 signals separately, because they
differ depending on the pull-up resistance and wiring capacity.
Remark 2. IICWL0: IICA low-level width setting register 0
IICWH0: ICA high-level width setting register 0
t
F
: SDAA0 and SCLA0 signal fall time
t
R
: SDAA0 and SCLA0 signal rise time
f
CLK
: CPU/peripheral hardware clock frequency
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