RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA
R01UH0959EJ0110 Rev.1.10 Page 594 of 765
Mar 7, 2023
Figure 13-32. Example of Slave to Master Communications
(8th Cycle Clock Stretching is Selected for Master, 9th Cycle Clock Stretching is Selected for Slave) (1/3)
(1) Start condition ~ address ~ data
IICA0
ACKD0
(ACK detection)
<1>
<2>
<5>
L
H
Note 2
AD5 AD4
Start condition
Master side
STT0
(ST trigger)
SPT0
(SP trigger)
WREL0
(release clock stretching)
INTIICA0
(interrupt)
TRC0
(transmission/reception)
Bus line
SCLA0 (bus)
(clock line)
SDAA0 (bus)
(data line)
AD6 AD3 AD2 AD1 AD0
D
1
7
Slave side
IICA0
ACKD0
(ACK detection)
<3>
<4>
H
H
L
<6>
Note 3
Slave address
STD0
(ST detection)
SPD0
(SP detection)
WTIM0
(Clock stretch timing control)
ACKE0
(ACK control)
MSTS0
(communication state)
WREL0
(release clock stretching)
INTIICA0
(interrupt)
TRC0
(transmission/reception)
WTIM0
(Clock stretch timing control)
ACKE0
(ACK control)
MSTS0
(communication state)
R
ACK
<7>
Note 1
L
: Clock stretching by the master
: Clock stretching by the master and slave
Note 1. To release clock stretching in reception by the master, write FFH to IICA0 or set the WREL0 bit.
Note 2. Make sure that the time between the fall of the SDAA0 pin signal and the fall of the SCLA0 pin signal is at
least 4.0 μs when standard mode is set and at least 0.6 μs when fast mode is set.
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