RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA
R01UH0959EJ0110 Rev.1.10 Page 593 of 765
Mar 7, 2023
Note 2. To release clock stretching in reception by the slave, write FFH to IICA0 or set the WREL0 bit.
The following describes the operations in Figure 13-31 (4) Data ~ restart condition ~ address. After the operations of
steps <7> and <8>, the operations of steps <i> to <iii> are performed. As a result, processing returns to the data
transmission procedure in step <3>.
<7> After data transfer is completed, because ACKE0 = 1 for the slave, an ACK is sent to the master by the
hardware. The ACK is detected by the master (ACKD0 = 1) at the rising edge of the 9th clock.
<8> The master and slave apply clock stretching (SCLA0 = 0) at the falling edge of the 9th clock, and both the
master and slave issue an interrupt (INTIICA0: transfer end interrupt).
The slave reads the received data and releases clock stretching (WREL0 = 1).
When the start condition trigger is set again by the
master (STT0 = 1), the bus clock line goes high (SCLA0 = 1),
the bus data line goes low (SDAA0 = 0) after the restart condition setup time has elapsed, and a start condition
(SDAA0 changes from 1 to 0 with SCLA0 = 1) is generated. After that, when the star
t condition is detected, the
master is ready for communications when the bus clock line goes low (SCLA0 = 0) after the hold time has elapsed.
hen the master writes the address + R/W (transmission) to the IICA shift register 0 (IICA0), the slave address is
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