RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA
R01UH0959EJ0110 Rev.1.10 Page 595 of 765
Mar 7, 2023
Note 3. To release clock stretching in transmission by the slave, write data to the IICA0 register instead of setting the
WREL0 bit.
Explanation of <1> to <7> in Figure 13-32 (1) Start condition ~ address ~ data is given below.
<1> When the start condition trigger is set by the master (STT0 = 1), the bus data line (SDAA0) goes low and a start
condition (SDAA0 changes from 1 to 0 with SCLA0 = 1) is generated. After that, when the start condition is
detected, the master enters the master communication state (MSTS0 = 1). It is ready for communications when
the bus clock line goes low (SCLA0 = 0) after the hold time has elapsed.
<2> When the master writes the address + R (reception) to IICA shift register 0 (IICA0), the slave address is
transmitted.
<3> In the slave, if the address received matches its local address (SVA0 value)
Note 1
, an ACK is sent to the master
by the hardware. The ACK is detected by the master (ACKD0 = 1) at the rising edge of the 9th clock.
<4> The master issues an interrupt (INTIICA0: address transmission end interrupt) at the falling edge of the 9th
clock. The slave with the matching address applies clock stretching (SCLA0 = 0) and issues an interrupt
(INTIICA0: address match interrupt)
Note 1
.
<5> The timing of clock stretching by the master is changed to the 8th clock (WTIM0 = 0).
<6> The slave writes transmit data to the IICA0 register and releases clock stretching by the slave.
<7> The master releases clock stretching (WREL0 = 1) and starts data transfer with the slave.
Note 1. If the transmitted address does not match the address of the slave, the slave does not return an ACK to the
master (NACK: SDAA0 = 1). The slave also neither issue the INTIICA0 interrupt (address match interrupt) nor
apply clock stretching.
The master, however, issues the INTIICA0 interrupt (address transmission end interrupt) in response to an
ACK or NACK.
Remark <1> to <19> in Figure 13-32 represent a series of operation procedures for data communications via the I
2
C
bus.
Figure 13-32 (1) Start condition ~ address ~ data shows steps <1> to <7>.
Figure 13-32 (2) Address ~ data ~ data shows steps <3> to <12>.
Figure 13-32 (3) Data ~ data ~ stop condition shows steps <8> to <19>.
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