RL78/G15 CHAPTER 13 SERIAL INTERFACE IICA
R01UH0959EJ0110 Rev.1.10 Page 596 of 765
Mar 7, 2023
Figure 13-32. Example of Slave to Master Communications
(8th Cycle Clock Stretching is Selected for Master, 9th Cycle Clock Stretching is Selected for Slave) (2/3)
(2) Address ~ data ~ data
IICA0
ACKD0
(ACK detection)
<5>
L
H
D
1
6 D
1
5
Master side
STT0
(ST trigger)
SPT0
(SP trigger)
WREL0
(release clock stretching)
INTIICA0
(interrupt)
TRC0
(transmission/reception)
Bus line
SCLA0 (bus)
(clock line)
SDAA0 (bus)
(data line)
D
1
7 D
1
4 D
1
3 D
1
2 D
1
1
Slave side
IICA0
ACKD0
(ACK detection)
<10>
<8>
H
H
L
STD0
(ST detection)
SPD0
(SP detection)
WTIM0
(Clock stretch timing control)
ACKE0
(ACK control)
MSTS0
(communication state)
WREL0
(release clock stretching)
INTIICA0
(interrupt)
TRC0
(transmission/reception)
WTIM0
(Clock stretch timing control)
ACKE
0
(ACK control
)
MSTS0
(communication state)
D
1
0
H
L
<4>
<3>
L
R ACK
<7>
Note 1
<9>
L
L
<11>
ACK
<6>
Note 2
H
<12>
Note 2
D
2
7
: Clock stretching by the master
: Clock stretching by the slave
: Clock stretching by the master and slave
Note 1
Note 1. To release clock stretching in reception by the master, write FFH to IICA0 or set the WREL0 bit.
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