RL78/G15 CHAPTER 6 TIMER ARRAY UNIT
R01UH0959EJ0110 Rev.1.10 Page 277 of 765
Mar 7, 2023
Figure 6-73. Operation Procedure When PWM Function Is Used (1/2)
Software Operation Hardware Status
TAU
default
setting
Power-off status
(Clock supply is stopped and writing to each register
is disabled.)
Sets the TAUmEN bit of peripheral enable register 0
(PER0) to 1.
Power-on status. Each channel stops operating.
(Clock supply is started and writing to each register is
enabled.)
Sets timer clock select register m (TPSm).
Determines clock frequencies of CKm0 and CKm1.
Channel
default
setting
Sets timer mode register mn, mp (TMRmn, TMRmp)
of two channels to be used (determines operation
mode of channels).
An interval (period) value is set to timer data register
mn (TDRmn) of the master channel, and a duty factor
is set to the TDRmp register of the slave channel.
Channel stops operating.
(Clock is supplied and some power is consumed.)
Sets slave channel.
The TOMmp bit of timer output mode register m
(TOMm) is set to 1 (slave channel output mode).
Sets the TOLmp bit.
Sets the TOmp bit and determines default level of
the TOmp output.
The TOmp pin goes into Hi-Z output state.
The TOmp default setting level is output when the port
mode register is in output mode and the port register
is 0.
Sets the TOEmp bit to 1 and enables operation of
TOmp.
Clears the port register and port mode register to
0.
TOmp does not change because channel stops
operating.
The TOmp pin outputs the TOmp set level.
(Remark is listed on the next page.)
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