RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT
R01UH0959EJ0110 Rev.1.10 Page 425 of 765
Mar 7, 2023
(4) Processing flow (in continuous transmission/reception mode)
Figure 12-43. Timing Chart of Master Transmission/Reception (in Continuous Transmission/Reception Mode) (Type 1:
DAPmn = 0, CKPmn = 0)
Shift
register mn
SIp pin
SCKp pin
Data transmission/
reception
SSmn
STmn
SEmn
SDRmn
INTCSIp
TSFmn
Transmit data
1
Transmit data 2 Receive data 2
Receive data 3
BFFmn
MDmn0
<
1
>
<8>
<5
>
<
3> <3>
<4
> <3>
<6>
Receive data 1 Transmit data 3
Receive data 3
<4> <7
>
Read Read
Reception & shift operation
Transmit data
3
SOp pin
<2>
<2> <2
>
Note
1 Note 2 Note 2
Receive data 2Receive data
1
Transmit data 1
Transmit data 2
Data transmission/receptionData transmission/reception
Reception & shift operation Reception
&
shift operation
Write
Write Write
Read
Note 1. If transmit data is written to the SDRmn register while the BFFmn bit of serial status register mn (SSRmn) is 1
(valid data is stored in serial data register mn (SDRmn)), the transmit data is overwritten.
Note 2. The transmit data can be read by reading the SDRmn register during this period. Reading this register does
not affect the transfer operation.
Caution The MDmn0 bit of serial mode register mn (SMRmn) can be rewritten even during operation.
However, rewrite it before transfer of the last bit is started, so that it has been rewritten before the
transfer end interrupt of the last transmit data.
Remark 1. <1> to <8> in the figure correspond to <1> to <8> in Figure 12-44 Flowchart of Master
Transmission/Reception (in Continuous Transmission/Reception Mode).
Remark 2. m: Unit number (m = 0), n: Channel number (n = 0, 1), p: CSI number (p = 00, 01), mn = 00, 01
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