Microchip Technology dsPIC30F - Page 732

Index
DS70046C-page 2 © 2004 Microchip Technology Inc.
Single Output Pulse Setup and
Interrupt Servicing..........................................14-12
Single Row Programming ........................................5-13
CODEC Interface Basics and Terminology......................22-8
Complementary PWM Output Mode ..............................15-24
Configuration Bit Descriptions..........................................24-7
BOR and POR .........................................................24-7
General Code Segment ...........................................24-7
Motor Control PWM Module.....................................24-7
Oscillator ..................................................................24-7
Connection Considerations ............................................ 17-47
Connectivity Development Board...................................25-14
Control Register Descriptions ..........................................3-18
Control Registers .......................................... 12-6, 17-4, 18-4
Assignment of Interrupts ..........................................6-14
Controlling Sample/Conversion Operation.....................17-29
Controlling Sample/Conversion Operation (12-bit) ........18-19
Conversion Sequence Examples ...................................17-31
Conversion Sequence Examples (12-bit).......................18-21
CPU
Register Maps..........................................................2-38
Related Application Notes........................................2-40
Revision History .......................................................2-41
CPU Clocking Scheme.......................................................7-4
CPU Priority Status ............................................................6-5
CPU Register Descriptions ..............................................2-11
Crystal Oscillators, Ceramic Resonators .........................7-10
D
Data Accumulator
Status Bits................................................................2-23
Data Accumulator Adder/Subtractor ................................2-23
Data Accumulators...........................................................2-20
Data Alignment...................................................................3-7
Data EEPROM Programming ..........................................5-14
Erasing One Row.....................................................5-18
Erasing One Word ...................................................5-16
Reading Memory......................................................5-20
Row Algorithm..........................................................5-15
Single Word Algorithm .............................................5-15
Write One Row.........................................................5-19
Writing One Word ....................................................5-17
Data Memory
Map ............................................................................3-3
Near ...........................................................................3-4
Data Space Address
Generator Units (AGUs).............................................3-5
X Address Generator Unit..........................................3-5
Y Address Generator Unit..........................................3-5
Data Space Write Saturation............................................2-24
DCI
Buffer Control Unit .................................................22-13
Control Register Descriptions ..................................22-2
Operation ...............................................................22-10
Using the Module ................................................... 22-17
Dead Time Control .........................................................15-25
Determining Best Values for Crystals,
Clock Mode, C1, C2, and Rs ...................................7-12
Device Configuration
Register Descriptions...............................................24-2
Device Identification Registers.........................................24-8
Device ID (DEVID) ...................................................24-8
Unit ID Field .............................................................24-8
Device Reset Times.........................................................8-11
Device Start-up Time Lines..............................................8-13
Device Wake-up on Sleep/Idle.......................................13-10
Disable Interrupts Instruction ............................................. 6-8
Divide Support ................................................................. 2-27
DSP Algorithm Library ..................................................... 25-7
DSP Engine ..................................................................... 2-18
DSP Engine Mode Selection ........................................... 2-26
DSP Engine Trap Events................................................. 2-26
DSP Filter Design Software Utility ................................... 25-8
dsPIC Language Suite..................................................... 25-3
dsPIC30F Hardware Development Boards.................... 25-11
E
Equations
Calculating the PWM Period.................................. 14-19
Calculation for Maximum PWM Resolution ........... 14-20
Modulo End Address for Incrementing Buffer............ 3-9
Modulo Start Address for Decrementing Buffer......... 3-9
WDT Time-out Period.............................................. 10-7
External Clock Input......................................................... 7-13
External Interrupt Support................................................ 6-10
External RC Oscillator ..................................................... 7-14
Operating Frequency............................................... 7-15
Start-up.................................................................... 7-15
with I/O Enabled ...................................................... 7-15
External Reset (EXTR) ...................................................... 8-7
F
Fail-Safe Clock Monitor (FSCM)...................................... 7-20
and Slow Oscillator Start-up .................................... 7-21
and WDT ................................................................. 7-21
Delay ....................................................................... 7-20
Flash and Data EEPROM Programming
Control Registers....................................................... 5-5
NVMADR ........................................................... 5-6
NVMCON........................................................... 5-5
NVMKEY ........................................................... 5-6
Flash Program Memory
Erasing a Row ......................................................... 5-11
Loading Write Latches............................................. 5-12
Programming Algorithm........................................... 5-10
FSCM
and Device Resets................................................... 8-12
Delay for Crystal and PLL Clock Sources................ 8-12
G
General Purpose Development Board........................... 25-12
H
Hard Traps......................................................................... 6-7
Address Error (Level 13)............................................ 6-8
Oscillator Failure (Level 14)....................................... 6-8
Priority and Conflicts.................................................. 6-7
Stack Error (Level 12)................................................ 6-6
How to Start Sampling (12-bit)....................................... 18-14
How to Start Sampling and Start Conversions (12-bit) .. 18-14
I
I/O Multiplexing with Multiple Peripherals ........................ 11-4
I/O Pin Control ..............................12-22, 13-10, 14-23, 16-18
I/O Port Control Registers................................................ 11-3
I/O Ports
Related Application Notes ....................................... 11-9
Revision History..................................................... 11-10
I
2
C
Acknowledge Generation....................................... 21-21
Building Complete Master Messages .................... 21-24