Microchip Technology dsPIC30F - Page 733

© 2004 Microchip Technology Inc. DS70046C-page 3
dsPIC30F Family Reference Manual
Index
Bus Arbitration and Bus Collision........................... 21-30
Bus Collision During a Repeated
Start Condition ............................................... 21-31
Bus Collision During a Start Condition................... 21-31
Bus Collision During a Stop Condition ................... 21-31
Bus Collision During Message Bit Transmission ...21-31
Bus Connection Considerations............................. 21-47
Communicating as a Master in a Multi-Master
Environment................................................... 21-29
Communicating as a Slave .................................... 21-32
Detecting Bus Collisions and Resending
Messages ...................................................... 21-30
Detecting Start and Stop Conditions...................... 21-32
Detecting the Address............................................ 21-33
Enabling I/O ........................................................... 21-13
Enabling Operation ................................................ 21-13
Generating Repeated Start Bus Event................... 21-23
Generating Start Bus Event ................................... 21-16
Generating Stop Bus Event ................................... 21-22
Initiating and Terminating Data Transfer.................. 26-3
Interrupts................................................................ 21-13
Master Message Protocol States ........................... 21-24
Module Operation during PWRSAV Instruction .....21-49
Receiving Data from a Master Device ...................21-37
Receiving Data from a Slave Device ..................... 21-19
Sending Data to a Master Device .......................... 21-44
Sending Data to a Slave Device ............................ 21-17
Start ......................................................................... 26-3
Stop.......................................................................... 26-3
I
2
C Module
10-bit Address Mode.............................................. 21-35
Multi-master Mode ................................................. 21-29
Idle Mode ......................................................................... 10-4
Time Delays on Wake-up from ................................10-5
Wake-up from on Interrupt ....................................... 10-5
Wake-up from on Reset ........................................... 10-5
Wake-up from on WDT Time-out ............................. 10-5
Independent PWM Output Mode ................................... 15-28
Initialization .................................................................... 17-48
Initialization (12-bit)........................................................ 18-29
Input Capture
Associated Special Function Registers.................. 13-11
Buffer Not Empty (ICBNE) ....................................... 13-9
Design Tips ............................................................ 13-12
Interrupts.................................................................. 13-9
Control Bits ...................................................... 13-9
Operation in Power Saving States ......................... 13-10
Overflow (ICOV)....................................................... 13-9
Related Application Notes...................................... 13-13
Input Capture Event Modes ............................................. 13-4
Input Capture Registers ................................................... 13-3
Instruction Flow Types ..................................................... 2-27
Instruction Stall Cycles..................................................... 2-36
Internal Fast RC Oscillator (FRC) .................................... 7-19
Internal Low Power RC (LPRC) Oscillator ....................... 7-20
Enabling ................................................................... 7-20
Internal Voltage Reference ................................................ 9-3
Interrupt Control and Status Registers............................. 6-14
CORCON ................................................................. 6-14
IECx ......................................................................... 6-14
IFSx.......................................................................... 6-14
INTCON1, INTCON2 ............................................... 6-14
IPCx ......................................................................... 6-14
SR ............................................................................ 6-14
Interrupt Controller
Associated Special Function Registers.................... 6-43
Interrupt Latency
One-Cycle Instructions ............................................ 6-11
Two-Cycle Instructions ............................................ 6-12
Interrupt Operation ............................................................ 6-9
Nesting .................................................................... 6-10
Return From Interrupt ................................................ 6-9
Interrupt Priority ................................................................. 6-5
Interrupt Processing Timing............................................. 6-11
Interrupt Setup Procedures.............................................. 6-42
Initialization.............................................................. 6-42
Interrupt Disable ...................................................... 6-42
Interrupt Service Routine......................................... 6-42
Trap Service Routine............................................... 6-42
Interrupt Vector Table........................................................ 6-2
Interrupts
Design Tips.............................................................. 6-44
Related Application Notes ....................................... 6-45
Revision History....................................................... 6-46
Interrupts Coincident with Power Save Instructions ........ 10-5
Introduction
Revision History......................................................... 1-7
IWCOL........................................................................... 21-22
L
LAT (I/O Latch) Registers................................................ 11-3
Loop Constructs .............................................................. 2-30
DO ........................................................................... 2-32
REPEAT .................................................................. 2-30
Low Power 32 kHz Crystal Oscillator............................... 7-19
Low Power 32 kHz Crystal Oscillator Input.................... 12-15
LP Oscillator
Continuous Operation.............................................. 7-19
Enable ..................................................................... 7-19
Intermittent Operation.............................................. 7-19
Operation with Timer1 ............................................. 7-19
LVD
Control Bits ................................................................ 9-3
Current Consumption for Operation .......................... 9-5
Design Tips................................................................ 9-6
Initialization Steps...................................................... 9-5
Operation................................................................... 9-5
Operation During Sleep and Idle Mode ..................... 9-5
Related Application Notes ......................................... 9-7
Trip Point Selection ................................................... 9-3
M
Math Library..................................................................... 25-7
Microchip Hardware and Language Tools....................... 25-2
Modes of Operation ......................................................... 14-4
Compare Mode Output Driven High ........................ 14-5
Compare Mode Output Driven Low ......................... 14-6
Compare Mode Toggle Output ................................ 14-7
Dual Compare Match............................................... 14-9
Dual Compare, Continuous Output Pulses............ 14-14
Dual Compare, Generating Continuous
Output Pulses Special Cases (table)............. 14-17
Dual Compare, Single Output Pulse........................ 14-9
Special Cases (table) .................................... 14-13
Single Compare Match ............................................ 14-4
Modulo Addressing............................................................ 3-7
Applicability.............................................................. 3-11
Calculation................................................................. 3-9
Initialization for Decrementing Buffer....................... 3-13
Initialization for Incrementing Modulo Buffer ........... 3-12
Start and End Address Selection............................... 3-8
W Address Register Selection................................... 3-9