NXP Semiconductors MC9S12G - Page 115

Device Overview MC9S12G-Family
MC9S12G Family Reference Manual Rev.1.27
NXP Semiconductors 117
Table 1-27. 64-Pin LQFP Pinout for S12G192 and S12G240
Function
<----lowest-----PRIORITY-----highest---->
Power
Supply
Internal Pull
Resistor
Package Pin Pin
2nd
Func.
3rd
Func.
4th
Func
5th
Func
CTRL
Reset
State
1 PJ6 KWJ6 SCK2 — — V
DDX
PERJ/PPSJ Up
2 PJ5 KWJ5 MOSI2 — — V
DDX
PERJ/PPSJ Up
3 PJ4 KWJ4 MISO2 — — V
DDX
PERJ/PPSJ Up
4 RESET — — — — V
DDX
PULLUP
5 VDDX — — — — — — —
6 VDDR — — — — — — —
7 VSSX — — — — — — —
8 PE0
1
EXTAL — — — V
DDX
PUCR/PDPEE Down
9 VSS — — — — — — —
10 PE1
1
XTAL — — — V
DDX
PUCR/PDPEE Down
11 TEST — — — — N.A. RESET
pin Down
12 PJ0 KWJ0 MISO1 — — V
DDX
PERJ/PPSJ Up
13 PJ1 KWJ1 MOSI1 — — V
DDX
PERJ/PPSJ Up
14 PJ2 KWJ2 SCK1 — — V
DDX
PERJ/PPSJ Up
15 PJ3 KWJ3 SS1
——V
DDX
PERJ/PPSJ Up
16 BKGD MODC — — — V
DDX
PUCR/BKPUE Up
17 PP0 KWP0 ETRIG0 API_EXTC
LK
PWM0 V
DDX
PERP/PPSP Disabled
18 PP1 KWP1 ETRIG1 ECLKX2 PWM1 V
DDX
PERP/PPSP Disabled
19 PP2 KWP2 ETRIG2 PWM2 — V
DDX
PERP/PPSP Disabled
20 PP3 KWP3 ETRIG3 PWM3 — V
DDX
PERP/PPSP Disabled
21 PP4 KWP4 PWM4 — — V
DDX
PERP/PPSP Disabled
22 PP5 KWP5 PWM5 — — V
DDX
PERP/PPSP Disabled
23 PP6 KWP6 PWM6 — — V
DDX
PERP/PPSP Disabled
24 PP7 KWP7 PWM7 — — V
DDX
PERP/PPSP Disabled
25 PT7 IOC7 — — — V
DDX
PERT/PPST Disabled
26 PT6 IOC6 — — — V
DDX
PERT/PPST Disabled
27 PT5 IOC5 — — — V
DDX
PERT/PPST Disabled