NXP Semiconductors MC9S12G User Manual

S12 Clock, Reset and Power Management Unit (S12CPMU)
MC9S12G Family Reference Manual Rev.1.27
358 NXP Semiconductors
10.1.3 S12CPMU Block Diagram
Figure 10-1. Block diagram of S12CPMU
S12CPMU
EXTAL
XTAL
System Reset
Power-On Detect
PLL Lock Interrupt
MMC
Illegal Address Access
COP time out
Loop
Reference
Divider
COP
Watchdog
Voltage
VDDR
Internal
Reset
Generator
Divide by
Phase
Post
Divider
1,2,.,32
VCOCLK
ECLK2X
LOCKIE
IRCTRIM[9:0]
SYNDIV[5:0]
LOCK
REFDIV[3:0]
2*(SYNDIV+1)
Pierce
Oscillator
4MHz-16MHz
OSCE
ILAF
PORF
divide
by 2
ECLK
POSTDIV[4:0]
Power-On Reset
Controlled
locked
Loop with
internal
Filter (PLL)
REFCLK
FBCLK
REFFRQ[1:0]
VCOFRQ[1:0]
Lock
detect
Regulator
3.13 to 5.5V
Autonomous
Periodic
Interrupt (API)
API Interrupt
VDDA
VSSA
PLLSEL
(to MSCAN)
VDDX
VSSX
VSS
Low Voltage Detect VDDX
LVRF
PLLCLK
Reference
divide
by 8
BDM Clock
Clock
(IRC1M)
Clock
Monitor
monitor fail
Real Time
Interrupt (RTI)
RTI Interrupt
PSTP
CPMURTI
Oscillator status Interrupt
(XOSCLCP)
CAN_OSCCLK
Low Voltage Interrupt
ACLK
APICLK
RTICLK
IRCCLK
OSCCLK
RTIOSCSEL
CPMUCOP
COPCLK
IRCCLK
OSCCLK
COPOSCSEL0
to Reset
Generator
COP time out
PCE
PRE
UPOSC=0 sets PLLSEL bit
API_EXTCLK
RC
Osc.
VDD, VDDF
(core supplies)
UPOSC
RESET
OSCIE
APIE
RTIE
LVDS LVIE
Low Voltage Detect VDDA
UPOSC
UPOSC=0 clears
&
OSCCLK
divide
by 4
Bus Clock
IRCCLK
(to LCD)
ACLK
COPOSCSEL1
(Bus Clock)
(Core Clock)
OSCCLK_LCP
External

NXP Semiconductors MC9S12G Specifications

General

Brand	NXP Semiconductors
Model	MC9S12G
Category	Microcontrollers
Language	English