NXP Semiconductors MC9S12G - Features

Digital Analog Converter (DAC_8B5V)
MC9S12G Family Reference Manual Rev.1.27
560 NXP Semiconductors
The configuration registers provide all required control bits for the DAC resistor network and for the
operational amplifier.
The DAC resistor network generates the desired analog output voltage. The unbuffered voltage from the
DAC resistor network output can be routed to the external DACU pin. When enabled, the buffered voltage
from the operational amplifier output is available on the external AMP pin.
The operational amplifier is also stand alone usable.
Figure 17-1 shows the block diagram of the DAC_8B5V module.
17.2.1 Features
The DAC_8B5V module includes these distinctive features:
• 1 digital-analog converter channel with:
— 8 bit resolution
— full and reduced output voltage range
— buffered or unbuffered analog output voltage usable
• operational amplifier stand alone usable
17.2.2 Modes of Operation
The DAC_8B5V module behaves as follows in the system power modes:
1. CPU run mode
The functionality of the DAC_8B5V module is available.
2. CPU stop mode
Independent from the mode settings, the operational amplifier is disabled, switch S1 and S2 are
open.
If the “Unbuffered DAC” mode was used before entering stop mode, then the DACU pin will reach
VRH voltage level during stop mode.
The content of the configuration registers is unchanged.
NOTE
After enabling and after return from CPU stop mode, the DAC_8B5V
module needs a settling time to get fully operational, see Settling time
specification of dac_8b5V_analog_ll18.