NXP Semiconductors MC9S12G User Manual

Device Overview MC9S12G-Family
MC9S12G Family Reference Manual Rev.1.27
NXP Semiconductors 145
1.14 Autonomous Clock (ACLK) Configuration
The autonomous clock
1
(ACLK) is not factory trimmed. The reset value of the autonomous clock
trimming register
2
(CPMUACLKTR) is 0xFC.
1.15 ADC External Trigger Input Connection
The ADC module includes external trigger inputs ETRIG0, ETRIG1, ETRIG2, and ETRIG3. The external
trigger allows the user to synchronize ADC conversion to external trigger events. Chapter 2, “Port
Integration Module (S12GPIMV1)” describes the connection of the external trigger inputs. Consult the
ADC section for information about the analog-to-digital converter module. References to freeze mode are
equivalent to active BDM mode.
1.16 ADC Special Conversion Channels
Whenever the ADC’s Special Channel Conversion Bit (SC) is set, it is capable of running conversion on
a number of internal channels (see Table 13-15). Table 1-38 lists the internal reference voltages which are
connected to these special conversion channels.
Table 1-37. Initial WCOP Configuration
NV[3] in
FOPT Register
WCOP in
CPMUCOP Register
10
01
1. See Chapter 10, “S12 Clock, Reset and Power Management Unit (S12CPMU)”
2. See Section 10.3.2.15, “Autonomous Clock Trimming Register (CPMUACLKTR)”
Table 1-38. Usage of ADC Special Conversion Channels
ADC Channel Usage
Internal_0 V
DDF
1
1
See Section 1.17, “ADC Result Reference”.
Internal_1 unused
Internal_2 unused
Internal_3 unused
Internal_4 unused
Internal_5 unused
Internal_6
unused
Temperature sense of ADC
hardmacro
2
2
The ADC temperature sensor is only available on S12GA192 and
S12GA240 devices.
Internal_7 unused

NXP Semiconductors MC9S12G Specifications

General

Brand	NXP Semiconductors
Model	MC9S12G
Category	Microcontrollers
Language	English