NXP Semiconductors MC9S12G - A.15 SPI Timing

Electrical Characteristics
MC9S12G Family Reference Manual Rev.1.27
NXP Semiconductors 1227
A.15 SPI Timing
This section provides electrical parametrics and ratings for the SPI. In Table A-50 the measurement
conditions are listed.
A.15.1 Master Mode
In Figure A-7 the timing diagram for master mode with transmission format CPHA = 0 is depicted.
Figure A-7. SPI Master Timing (CPHA = 0)
Table A-50. Measurement Conditions
Conditions are 4.5 V < V
DD35
< 5.5 V junction temperature from –40C to T
Jmax
Description Value Unit
Drive mode Full drive mode —
Load capacitance C
LOAD
1
,
on all outputs
1
Timing specified for equal load on all SPI output pins. Avoid asymmetric load.
50 pF
Thresholds for delay measurement points (35% / 65%) V
DDX
V
SCK
(Output)
SCK
(Output)
MISO
(Input)
MOSI
(Output)
SS
(Output)
1
9
5 6
MSB IN2
Bit MSB-1. . . 1
LSB IN
MSB OUT2
LSB OUT
Bit MSB-1. . . 1
11
4
4
2
10
(CPOL = 0)
(CPOL = 1)
3
13
13
1. If configured as an output.
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, bit 2... MSB.
12
12