NXP Semiconductors MC9S12G - Register Descriptions

Serial Peripheral Interface (S12SPIV5)
MC9S12G Family Reference Manual Rev.1.27
NXP Semiconductors 695
21.3.2 Register Descriptions
This section consists of register descriptions in address order. Each description includes a standard register
diagram with an associated figure number. Details of register bit and field function follow the register
diagrams, in bit order.
21.3.2.1 SPI Control Register 1 (SPICR1)
Read: Anytime
Write: Anytime
0x0005
SPIDRL
RR7R6R5R4R3R2R1R0
T7 T6 T5 T4 T3 T2 T1 T0W
0x0006
Reserved
R
W
0x0007
Reserved
R
W
Module Base +0x0000
76543210
R
SPIE SPE SPTIE MSTR CPOL CPHA SSOE LSBFE
W
Reset00000100
Figure 21-3. SPI Control Register 1 (SPICR1)
Table 21-1. SPICR1 Field Descriptions
Field Description
7
SPIE
SPI Interrupt Enable Bit — This bit enables SPI interrupt requests, if SPIF or MODF status flag is set.
0 SPI interrupts disabled.
1 SPI interrupts enabled.
6
SPE
SPI System Enable Bit — This bit enables the SPI system and dedicates the SPI port pins to SPI system
functions. If SPE is cleared, SPI is disabled and forced into idle state, status bits in SPISR register are reset.
0 SPI disabled (lower power consumption).
1 SPI enabled, port pins are dedicated to SPI functions.
5
SPTIE
SPI Transmit Interrupt Enable — This bit enables SPI interrupt requests, if SPTEF flag is set.
0 SPTEF interrupt disabled.
1 SPTEF interrupt enabled.
Register
Name
Bit 76 5 4 3 2 1Bit 0
= Unimplemented or Reserved
Figure 21-2. SPI Register Summary