NXP Semiconductors MC9S12G - Interrupts

S12 Clock, Reset and Power Management Unit (S12CPMU)
MC9S12G Family Reference Manual Rev.1.27
398 NXP Semiconductors
10.6 Interrupts
The interrupt/reset vectors requested by the S12CPMU are listed in Table 10-29. Refer to MCU
specification for related vector addresses and priorities.
10.6.1 Description of Interrupt Operation
10.6.1.1 Real Time Interrupt (RTI)
The clock source for the RTI is either IRCCLK or OSCCLK depending on the setting of the RTIOSCSEL
bit. In Stop Mode with PSTP=1 (Pseudo Stop Mode), RTIOSCSEL=1 and PRE=1 the RTI continues to
run, else the RTI counter halts in Stop Mode.
The RTI can be used to generate hardware interrupts at a fixed periodic rate. If enabled (by setting
RTIE=1), this interrupt will occur at the rate selected by the CPMURTI register. At the end of the RTI
time-out period the RTIF flag is set to one and a new RTI time-out period starts immediately.
A write to the CPMURTI register restarts the RTI time-out period.
10.6.1.2 PLL Lock Interrupt
The S12CPMU generates a PLL Lock interrupt when the lock condition (LOCK status bit) of the PLL
changes, either from a locked state to an unlocked state or vice versa. Lock interrupts are locally disabled
by setting the LOCKIE bit to zero. The PLL Lock interrupt flag (LOCKIF) is set to 1 when the lock
condition has changed, and is cleared to 0 by writing a 1 to the LOCKIF bit.
10.6.1.3 Oscillator Status Interrupt
When the OSCE bit is 0, then UPOSC stays 0. When OSCE = 1 the UPOSC bit is set after the LOCK bit
is set.
Upon detection of a status change (UPOSC) the OSCIF flag is set. Going into Full Stop Mode or disabling
the oscillator can also cause a status change of UPOSC.
Table 10-29. S12CPMU Interrupt Vectors
Interrupt Source
CCR
Mask
Local Enable
RTI time-out interrupt I bit CPMUINT (RTIE)
PLL lock interrupt I bit CPMUINT (LOCKIE)
Oscillator status
interrupt
I bit CPMUINT (OSCIE)
Low voltage interrupt I bit CPMULVCTL (LVIE)
Autonomous
Periodical Interrupt
I bit CPMUAPICTL (APIE)