240 KByte Flash Module (S12FTMRG240K2V1)
MC9S12G Family Reference Manual Rev.1.27
1152 NXP Semiconductors
• VERNUM: Version number. The first version is number 0b_0001 with both 0b_0000 and 0b_1111
meaning ‘none’.
31.4.3 Internal NVM resource (NVMRES)
IFR is an internal NVM resource readable by CPU , when NVMRES is active. The IFR fields are shown
in Table 31-5.
The NVMRES global address map is shown in Table 31-6.
For FTMRG240K2 the NVMRES address area is shared with 16K space of P-Flash area, as shown in
Figure 31-2.
31.4.4 Flash Command Operations
Flash command operations are used to modify Flash memory contents.
The next sections describe:
• How to write the FCLKDIV register that is used to generate a time base (FCLK) derived from
BUSCLK for Flash program and erase command operations
• The command write sequence used to set Flash command parameters and launch execution
• Valid Flash commands available for execution, according to MCU functional mode and MCU
security state.
31.4.4.1 Writing the FCLKDIV Register
Prior to issuing any Flash program or erase command after a reset, the user is required to write the
FCLKDIV register to divide BUSCLK down to a target FCLK of 1 MHz. Table 31-8 shows recommended
values for the FDIV field based on BUSCLK frequency.
NOTE
Programming or erasing the Flash memory cannot be performed if the bus
clock runs at less than 0.8 MHz. Setting FDIV too high can destroy the Flash
memory due to overstress. Setting FDIV too low can result in incomplete
programming or erasure of the Flash memory cells.
When the FCLKDIV register is written, the FDIVLD bit is set automatically. If the FDIVLD bit is 0, the
FCLKDIV register has not been written since the last reset. If the FCLKDIV register has not been written,
any Flash program or erase command loaded during a command write sequence will not execute and the
ACCERR bit in the FSTAT register will set.
31.4.4.2 Command Write Sequence
The Memory Controller will launch all valid Flash commands entered using a command write sequence.
Before launching a command, the ACCERR and FPVIOL bits in the FSTAT register must be clear (see
Section 31.3.2.7) and the CCIF flag should be tested to determine the status of the current command write
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