NXP Semiconductors MC9S12G - Detailed Signal Descriptions

Device Overview MC9S12G-Family
MC9S12G Family Reference Manual Rev.1.27
46 NXP Semiconductors
NOTE
To avoid current drawn from floating inputs, the input buffers of all
non-bonded pins are disabled.
1.7.2 Detailed Signal Descriptions
This section describes the signal properties. The relation between signals and package pins is described in
section 1.8 Device Pinouts.
1.7.2.1 RESET — External Reset Signal
The RESET signal is an active low bidirectional control signal. It acts as an input to initialize the MCU to
a known start-up state, and an output when an internal MCU function causes a reset. The RESET pin has
an internal pull-up device.
1.7.2.2 TEST — Test Pin
This input only pin is reserved for factory test. This pin has an internal pull-down device.
NOTE
The TEST pin must be tied to ground in all applications.
1.7.2.3 BKGD / MODC — Background Debug and Mode Pin
The BKGD/MODC pin is used as a pseudo-open-drain pin for the background debug communication. It
is used as a MCU operating mode select pin during reset. The state of this pin is latched to the MODC bit
at the rising edge of RESET
. The BKGD pin has an internal pull-up device.
1.7.2.4 EXTAL, XTAL — Oscillator Signal
EXTAL and XTAL are the crystal driver and external clock signals. On reset all the device clocks are
derived from the internal reference clock. XTAL is the oscillator output.
1.7.2.5 PAD[15:0] / KWAD[15:0] — Port AD Input Pins of ADC
PAD[15:0] are general-purpose input or output signals. These signals can have a pull-up or pull-down
device selected and enabled on per signal basis. Out of reset the pull devices are disabled.
Sum of Ports 142640548686
I/O Power Pairs VDDX/VSSX 1/1 1/1 1/1 1/1 3/3 3/3
Table 1-6. Port Availability by Package Option
Port 20 TSSOP 32 LQFP
48 LQFP
48 QFN
64 LQFP 100 LQFP KGD (Die)